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-rw-r--r--src/soc/rockchip/rk3288/clock.c161
-rw-r--r--src/soc/rockchip/rk3288/crypto.c20
-rw-r--r--src/soc/rockchip/rk3288/edp.c205
-rw-r--r--src/soc/rockchip/rk3288/gpio.c7
-rw-r--r--src/soc/rockchip/rk3288/i2c.c61
-rw-r--r--src/soc/rockchip/rk3288/pwm.c12
-rw-r--r--src/soc/rockchip/rk3288/sdram.c202
-rw-r--r--src/soc/rockchip/rk3288/software_i2c.c24
-rw-r--r--src/soc/rockchip/rk3288/spi.c22
-rw-r--r--src/soc/rockchip/rk3288/timer.c6
-rw-r--r--src/soc/rockchip/rk3288/tsadc.c12
-rw-r--r--src/soc/rockchip/rk3288/uart.c27
-rw-r--r--src/soc/rockchip/rk3288/vop.c59
13 files changed, 372 insertions, 446 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index d7420ea8d6..a9c888d631 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -217,19 +217,20 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
(div->no == 1 || !(div->no % 2)));
/* enter rest */
- writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]);
+ write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK));
- writel(RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT)
- | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)), &pll_con[0]);
+ write32(&pll_con[0],
+ RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)));
- writel(RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)), &pll_con[1]);
+ write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)));
- writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)), &pll_con[2]);
+ write32(&pll_con[2],
+ RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)));
udelay(10);
/* return form rest */
- writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]);
+ write32(&pll_con[3], RK_CLRBITS(PLL_RESET_MSK));
return 0;
}
@@ -257,9 +258,8 @@ void rkclk_init(void)
u32 pclk_div;
/* pll enter slow-mode */
- writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW)
- | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW));
/* init pll */
rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg);
@@ -267,7 +267,7 @@ void rkclk_init(void)
/* waiting for pll lock */
while (1) {
- if ((readl(&rk3288_grf->soc_status[1])
+ if ((read32(&rk3288_grf->soc_status[1])
& (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
== (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
break;
@@ -288,15 +288,8 @@ void rkclk_init(void)
assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
PD_BUS_ACLK_HZ && pclk_div < 0x7);
- writel(RK_SETBITS(PD_BUS_SEL_GPLL)
- | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK,
- pclk_div << PD_BUS_PCLK_DIV_SHIFT)
- | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK,
- hclk_div << PD_BUS_HCLK_DIV_SHIFT)
- | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK,
- aclk_div << PD_BUS_ACLK_DIV0_SHIFT)
- | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0),
- &cru_ptr->cru_clksel_con[1]);
+ write32(&cru_ptr->cru_clksel_con[1],
+ RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, pclk_div << PD_BUS_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, hclk_div << PD_BUS_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, aclk_div << PD_BUS_ACLK_DIV0_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0));
/*
* peri clock pll source selection and
@@ -313,33 +306,26 @@ void rkclk_init(void)
assert((1 << pclk_div) * PERI_PCLK_HZ ==
PERI_ACLK_HZ && (pclk_div < 0x4));
- writel(RK_SETBITS(PERI_SEL_GPLL)
- | RK_CLRSETBITS(PERI_PCLK_DIV_MSK,
- pclk_div << PERI_PCLK_DIV_SHIFT)
- | RK_CLRSETBITS(PERI_HCLK_DIV_MSK,
- hclk_div << PERI_HCLK_DIV_SHIFT)
- | RK_CLRSETBITS(PERI_ACLK_DIV_MSK,
- aclk_div << PERI_ACLK_DIV_SHIFT),
- &cru_ptr->cru_clksel_con[10]);
+ write32(&cru_ptr->cru_clksel_con[10],
+ RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, pclk_div << PERI_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, hclk_div << PERI_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, aclk_div << PERI_ACLK_DIV_SHIFT));
/* PLL enter normal-mode */
- writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM)
- | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM));
}
void rkclk_configure_cpu(void)
{
/* pll enter slow-mode */
- writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg);
/* waiting for pll lock */
while (1) {
- if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK)
+ if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK)
break;
udelay(1);
}
@@ -350,24 +336,19 @@ void rkclk_configure_cpu(void)
* core clock select apll, apll clk = 1800MHz
* arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
*/
- writel(RK_CLRBITS(CORE_SEL_PLL_MSK)
- | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT)
- | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT)
- | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0),
- &cru_ptr->cru_clksel_con[0]);
+ write32(&cru_ptr->cru_clksel_con[0],
+ RK_CLRBITS(CORE_SEL_PLL_MSK) | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0));
/*
* set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
* l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
*/
- writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0)
- | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT))
- | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)),
- &cru_ptr->cru_clksel_con[37]);
+ write32(&cru_ptr->cru_clksel_con[37],
+ RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)));
/* PLL enter normal-mode */
- writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM));
}
void rkclk_configure_ddr(unsigned int hz)
@@ -392,21 +373,21 @@ void rkclk_configure_ddr(unsigned int hz)
}
/* pll enter slow-mode */
- writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW));
rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg);
/* waiting for pll lock */
while (1) {
- if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK)
+ if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK)
break;
udelay(1);
}
/* PLL enter normal-mode */
- writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM));
}
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
@@ -417,22 +398,16 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
u32 phy_psrstn_shift = 1 + 5 * ch;
u32 phy_srstn_shift = 5 * ch;
- writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
- phy << phy_ctl_srstn_shift)
- | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift)
- | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift)
- | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift)
- | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift),
- &cru_ptr->cru_softrst_con[10]);
+ write32(&cru_ptr->cru_softrst_con[10],
+ RK_CLRSETBITS(1 << phy_ctl_srstn_shift, phy << phy_ctl_srstn_shift) | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift));
}
void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n)
{
u32 phy_ctl_srstn_shift = 4 + 5 * ch;
- writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift,
- n << phy_ctl_srstn_shift),
- &cru_ptr->cru_softrst_con[10]);
+ write32(&cru_ptr->cru_softrst_con[10],
+ RK_CLRSETBITS(1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift));
}
void rkclk_configure_spi(unsigned int bus, unsigned int hz)
@@ -443,19 +418,16 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
switch (bus) { /*select gpll as spi src clk, and set div*/
case 0:
- writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7
- | (src_clk_div - 1) << 0),
- &cru_ptr->cru_clksel_con[25]);
+ write32(&cru_ptr->cru_clksel_con[25],
+ RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0));
break;
case 1:
- writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15
- | (src_clk_div - 1) << 8),
- &cru_ptr->cru_clksel_con[25]);
+ write32(&cru_ptr->cru_clksel_con[25],
+ RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 | (src_clk_div - 1) << 8));
break;
case 2:
- writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7
- | (src_clk_div - 1) << 0),
- &cru_ptr->cru_clksel_con[39]);
+ write32(&cru_ptr->cru_clksel_con[39],
+ RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0));
break;
default:
printk(BIOS_ERR, "do not support this spi bus\n");
@@ -481,16 +453,15 @@ void rkclk_configure_i2s(unsigned int hz)
i2s0_outclk_sel: clk_i2s
i2s0_clk_sel: divider ouput from fraction
i2s0_pll_div_con: 0*/
- writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 ,
- 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0),
- &cru_ptr->cru_clksel_con[4]);
+ write32(&cru_ptr->cru_clksel_con[4],
+ RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0, 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
/* set frac divider */
v = clk_gcd(GPLL_HZ, hz);
n = (GPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == GPLL_HZ / n * d);
- writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]);
+ write32(&cru_ptr->cru_clksel_con[8], d << 16 | n);
}
void rkclk_configure_crypto(unsigned int hz)
@@ -499,8 +470,8 @@ void rkclk_configure_crypto(unsigned int hz)
assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ));
assert(hz <= 150*MHz); /* Suggested max in TRM. */
- writel(RK_CLRSETBITS(0x3 << 6, (div - 1) << 6),
- &cru_ptr->cru_clksel_con[26]);
+ write32(&cru_ptr->cru_clksel_con[26],
+ RK_CLRSETBITS(0x3 << 6, (div - 1) << 6));
}
void rkclk_configure_tsadc(unsigned int hz)
@@ -510,8 +481,8 @@ void rkclk_configure_tsadc(unsigned int hz)
div = src_clk / hz;
assert((div - 1 < 64) && (div * hz == 32 * KHz));
- writel(RK_CLRSETBITS(0x3f << 0, (div - 1) << 0),
- &cru_ptr->cru_clksel_con[2]);
+ write32(&cru_ptr->cru_clksel_con[2],
+ RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
}
static int pll_para_config(u32 freq_hz, struct pll_div *div)
@@ -579,12 +550,12 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
void rkclk_configure_edp(void)
{
/* clk_edp_24M source: 24M */
- writel(RK_SETBITS(1 << 15), &cru_ptr->cru_clksel_con[28]);
+ write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15));
/* rst edp */
- writel(RK_SETBITS(1 << 15), &cru_ptr->cru_softrst_con[6]);
+ write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15));
udelay(1);
- writel(RK_CLRBITS(1 << 15), &cru_ptr->cru_softrst_con[6]);
+ write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15));
}
void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
@@ -597,15 +568,13 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
switch (vop_id) {
case 0:
- writel(RK_CLRSETBITS(3 << 6 | 0x1f << 0,
- 0 << 6 | (div - 1) << 0),
- &cru_ptr->cru_clksel_con[31]);
+ write32(&cru_ptr->cru_clksel_con[31],
+ RK_CLRSETBITS(3 << 6 | 0x1f << 0, 0 << 6 | (div - 1) << 0));
break;
case 1:
- writel(RK_CLRSETBITS(3 << 14 | 0x1f << 8,
- 0 << 14 | (div - 1) << 8),
- &cru_ptr->cru_clksel_con[31]);
+ write32(&cru_ptr->cru_clksel_con[31],
+ RK_CLRSETBITS(3 << 14 | 0x1f << 8, 0 << 14 | (div - 1) << 8));
break;
}
}
@@ -618,34 +587,32 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
return -1;
/* npll enter slow-mode */
- writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW));
rkclk_set_pll(&cru_ptr->cru_npll_con[0], &npll_config);
/* waiting for pll lock */
while (1) {
- if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
+ if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
break;
udelay(1);
}
/* npll enter normal-mode */
- writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM),
- &cru_ptr->cru_mode_con);
+ write32(&cru_ptr->cru_mode_con,
+ RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM));
/* vop dclk source clk: npll,dclk_div: 1 */
switch (vop_id) {
case 0:
- writel(RK_CLRSETBITS(0xff << 8 | 3 << 0,
- 0 << 8 | 2 << 0),
- &cru_ptr->cru_clksel_con[27]);
+ write32(&cru_ptr->cru_clksel_con[27],
+ RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0));
break;
case 1:
- writel(RK_CLRSETBITS(0xff << 8 | 3 << 6,
- 0 << 8 | 2 << 6),
- &cru_ptr->cru_clksel_con[29]);
+ write32(&cru_ptr->cru_clksel_con[29],
+ RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6));
break;
}
return 0;
@@ -654,5 +621,5 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
int rkclk_was_watchdog_reset(void)
{
/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
- return readl(&cru_ptr->cru_glb_rst_st) & 0x30;
+ return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
}
diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c
index 20fd60a474..e57d1560e7 100644
--- a/src/soc/rockchip/rk3288/crypto.c
+++ b/src/soc/rockchip/rk3288/crypto.c
@@ -80,17 +80,17 @@ int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
}
- writel(RK_SETBITS(1 << 6), &crypto->ctrl); /* Assert HASH_FLUSH */
+ write32(&crypto->ctrl, RK_SETBITS(1 << 6)); /* Assert HASH_FLUSH */
udelay(1); /* for 10+ cycles to */
- writel(RK_CLRBITS(1 << 6), &crypto->ctrl); /* clear out old hash */
+ write32(&crypto->ctrl, RK_CLRBITS(1 << 6)); /* clear out old hash */
/* Enable DMA byte swapping for little-endian bus (Byteswap_??FIFO) */
- writel(1 << 5 | 1 << 4 | 1 << 3, &crypto->conf);
+ write32(&crypto->conf, 1 << 5 | 1 << 4 | 1 << 3);
- writel(HRDMA_ERR | HRDMA_DONE, &crypto->intena); /* enable interrupt */
+ write32(&crypto->intena, HRDMA_ERR | HRDMA_DONE); /* enable interrupt */
- writel(data_size, &crypto->hash_msg_len); /* program total size */
- writel(1 << 3 | 0x2, &crypto->hash_ctrl); /* swap DOUT, SHA256 */
+ write32(&crypto->hash_msg_len, data_size); /* program total size */
+ write32(&crypto->hash_ctrl, 1 << 3 | 0x2); /* swap DOUT, SHA256 */
printk(BIOS_DEBUG, "Initialized RK3288 HW crypto for %u byte SHA256\n",
data_size);
@@ -101,12 +101,12 @@ int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
{
uint32_t intsts;
- writel(HRDMA_ERR | HRDMA_DONE, &crypto->intsts); /* clear interrupts */
+ write32(&crypto->intsts, HRDMA_ERR | HRDMA_DONE); /* clear interrupts */
/* NOTE: This assumes that the DMA is reading from uncached SRAM. */
- writel((uint32_t)buf, &crypto->hrdmas);
- writel(size / sizeof(uint32_t), &crypto->hrdmal);
- writel(RK_SETBITS(1 << 3), &crypto->ctrl); /* Set HASH_START */
+ write32(&crypto->hrdmas, (uint32_t)buf);
+ write32(&crypto->hrdmal, size / sizeof(uint32_t));
+ write32(&crypto->ctrl, RK_SETBITS(1 << 3)); /* Set HASH_START */
do {
intsts = read32(&crypto->intsts);
if (intsts & HRDMA_ERR) {
diff --git a/src/soc/rockchip/rk3288/edp.c b/src/soc/rockchip/rk3288/edp.c
index 3f27195199..38e972d7cd 100644
--- a/src/soc/rockchip/rk3288/edp.c
+++ b/src/soc/rockchip/rk3288/edp.c
@@ -53,66 +53,52 @@ static const char *pre_emph_names[] = {
static void rk_edp_init_refclk(struct rk_edp *edp)
{
- writel(SEL_24M, &edp->regs->analog_ctl_2);
- writel(REF_CLK_24M, &edp->regs->pll_reg_1);
+ write32(&edp->regs->analog_ctl_2, SEL_24M);
+ write32(&edp->regs->pll_reg_1, REF_CLK_24M);
/*initial value*/
- writel(LDO_OUTPUT_V_SEL_145 |
- KVCO_DEFALUT |
- CHG_PUMP_CUR_SEL_5US |
- V2L_CUR_SEL_1MA, &edp->regs->pll_reg_2);
-
- writel(LOCK_DET_CNT_SEL_256 |
- LOOP_FILTER_RESET |
- PALL_SSC_RESET |
- LOCK_DET_BYPASS |
- PLL_LOCK_DET_MODE |
- PLL_LOCK_DET_FORCE, &edp->regs->pll_reg_3);
-
- writel(REGULATOR_V_SEL_950MV |
- STANDBY_CUR_SEL |
- CHG_PUMP_INOUT_CTRL_1200MV |
- CHG_PUMP_INPUT_CTRL_OP, &edp->regs->pll_reg_5);
-
- writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &edp->regs->ssc_reg);
-
- writel(TX_SWING_PRE_EMP_MODE |
- PRE_DRIVER_PW_CTRL1 |
- LP_MODE_CLK_REGULATOR |
- RESISTOR_MSB_CTRL |
- RESISTOR_CTRL, &edp->regs->tx_common);
-
- writel(DP_AUX_COMMON_MODE |
- DP_AUX_EN |
- AUX_TERM_50OHM, &edp->regs->dp_aux);
-
- writel(DP_BG_OUT_SEL |
- DP_DB_CUR_CTRL |
- DP_BG_SEL |
- DP_RESISTOR_TUNE_BG, &edp->regs->dp_bias);
-
- writel(CH1_CH3_SWING_EMP_CTRL |
- CH0_CH2_SWING_EMP_CTRL, &edp->regs->dp_reserv2);
+ write32(&edp->regs->pll_reg_2,
+ LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA);
+
+ write32(&edp->regs->pll_reg_3,
+ LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET | LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE);
+
+ write32(&edp->regs->pll_reg_5,
+ REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP);
+
+ write32(&edp->regs->ssc_reg, SSC_OFFSET | SSC_MODE | SSC_DEPTH);
+
+ write32(&edp->regs->tx_common,
+ TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 | LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL);
+
+ write32(&edp->regs->dp_aux,
+ DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM);
+
+ write32(&edp->regs->dp_bias,
+ DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG);
+
+ write32(&edp->regs->dp_reserv2,
+ CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL);
}
static void rk_edp_init_interrupt(struct rk_edp *edp)
{
/* Set interrupt pin assertion polarity as high */
- writel(INT_POL, &edp->regs->int_ctl);
+ write32(&edp->regs->int_ctl, INT_POL);
/* Clear pending registers */
- writel(0xff, &edp->regs->common_int_sta_1);
- writel(0x4f, &edp->regs->common_int_sta_2);
- writel(0xff, &edp->regs->common_int_sta_3);
- writel(0x27, &edp->regs->common_int_sta_4);
- writel(0x7f, &edp->regs->dp_int_sta);
+ write32(&edp->regs->common_int_sta_1, 0xff);
+ write32(&edp->regs->common_int_sta_2, 0x4f);
+ write32(&edp->regs->common_int_sta_3, 0xff);
+ write32(&edp->regs->common_int_sta_4, 0x27);
+ write32(&edp->regs->dp_int_sta, 0x7f);
/* 0:mask,1: unmask */
- writel(0x00, &edp->regs->common_int_mask_1);
- writel(0x00, &edp->regs->common_int_mask_2);
- writel(0x00, &edp->regs->common_int_mask_3);
- writel(0x00, &edp->regs->common_int_mask_4);
- writel(0x00, &edp->regs->int_sta_mask);
+ write32(&edp->regs->common_int_mask_1, 0x00);
+ write32(&edp->regs->common_int_mask_2, 0x00);
+ write32(&edp->regs->common_int_mask_3, 0x00);
+ write32(&edp->regs->common_int_mask_4, 0x00);
+ write32(&edp->regs->int_sta_mask, 0x00);
}
static void rk_edp_enable_sw_function(struct rk_edp *edp)
@@ -124,7 +110,7 @@ static int rk_edp_get_pll_lock_status(struct rk_edp *edp)
{
u32 val;
- val = readl(&edp->regs->dp_debug_ctl);
+ val = read32(&edp->regs->dp_debug_ctl);
return (val & PLL_LOCK) ? DP_PLL_LOCKED : DP_PLL_UNLOCKED;
}
@@ -132,9 +118,9 @@ static void rk_edp_init_analog_func(struct rk_edp *edp)
{
struct stopwatch sw;
- writel(0x00, &edp->regs->dp_pd);
+ write32(&edp->regs->dp_pd, 0x00);
- writel(PLL_LOCK_CHG, &edp->regs->common_int_sta_1);
+ write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG);
clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
@@ -156,13 +142,13 @@ static void rk_edp_init_analog_func(struct rk_edp *edp)
static void rk_edp_init_aux(struct rk_edp *edp)
{
/* Clear inerrupts related to AUX channel */
- writel(AUX_FUNC_EN_N, &edp->regs->dp_int_sta);
+ write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
/* Disable AUX channel module */
setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
- writel(DEFER_CTRL_EN | DEFER_COUNT(1), &edp->regs->aux_ch_defer_dtl);
+ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1));
/* Enable AUX channel module */
clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
@@ -175,7 +161,7 @@ static int rk_edp_aux_enable(struct rk_edp *edp)
setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN);
stopwatch_init_msecs_expire(&sw, 20);
do {
- if (!(readl(&edp->regs->aux_ch_ctl_2) & AUX_EN))
+ if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN))
return 0;
} while (!stopwatch_expired(&sw));
@@ -189,12 +175,12 @@ static int rk_edp_is_aux_reply(struct rk_edp *edp)
stopwatch_init_msecs_expire(&sw, 10);
- while (!(readl(&edp->regs->dp_int_sta) & RPLY_RECEIV)) {
+ while (!(read32(&edp->regs->dp_int_sta) & RPLY_RECEIV)) {
if (stopwatch_expired(&sw))
return -1;
}
- writel(RPLY_RECEIV, &edp->regs->dp_int_sta);
+ write32(&edp->regs->dp_int_sta, RPLY_RECEIV);
return 0;
}
@@ -216,14 +202,14 @@ static int rk_edp_start_aux_transaction(struct rk_edp *edp)
}
/* Clear interrupt source for AUX CH access error */
- val = readl(&edp->regs->dp_int_sta);
+ val = read32(&edp->regs->dp_int_sta);
if (val & AUX_ERR) {
- writel(AUX_ERR, &edp->regs->dp_int_sta);
+ write32(&edp->regs->dp_int_sta, AUX_ERR);
return -1;
}
/* Check AUX CH error access status */
- val = readl(&edp->regs->dp_int_sta);
+ val = read32(&edp->regs->dp_int_sta);
if ((val & AUX_STATUS_MASK) != 0) {
edp_debug("AUX CH error happens: %d\n\n",
val & AUX_STATUS_MASK);
@@ -249,15 +235,15 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp,
/* Clear AUX CH data buffer */
val = BUF_CLR;
- writel(val, &edp->regs->buf_data_ctl);
+ write32(&edp->regs->buf_data_ctl, val);
/* Select DPCD device address */
val = AUX_ADDR_7_0(val_addr);
- writel(val, &edp->regs->aux_addr_7_0);
+ write32(&edp->regs->aux_addr_7_0, val);
val = AUX_ADDR_15_8(val_addr);
- writel(val, &edp->regs->aux_addr_15_8);
+ write32(&edp->regs->aux_addr_15_8, val);
val = AUX_ADDR_19_16(val_addr);
- writel(val, &edp->regs->aux_addr_19_16);
+ write32(&edp->regs->aux_addr_19_16, val);
/*
* Set DisplayPort transaction and read 1 byte
@@ -269,13 +255,14 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp,
AUX_TX_COMM_DP_TRANSACTION |
AUX_TX_COMM_WRITE;
for (i = 0; i < len; i++)
- writel(*data++, &edp->regs->buf_data[i]);
+ write32(&edp->regs->buf_data[i],
+ *data++);
} else
val = AUX_LENGTH(len) |
AUX_TX_COMM_DP_TRANSACTION |
AUX_TX_COMM_READ;
- writel(val, &edp->regs->aux_ch_ctl_1);
+ write32(&edp->regs->aux_ch_ctl_1, val);
/* Start AUX transaction */
retval = rk_edp_start_aux_transaction(edp);
@@ -291,7 +278,7 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp,
if (request == DPCD_READ) {
for (i = 0; i < len; i++)
- *data++ = (u8)readl(&edp->regs->buf_data[i]);
+ *data++ = (u8)read32(&edp->regs->buf_data[i]);
}
length -= len;
@@ -357,7 +344,7 @@ static void rk_edp_set_link_training(struct rk_edp *edp,
int i;
for (i = 0; i < edp->link_train.lane_count; i++)
- writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
+ write32(&edp->regs->ln_link_trn_ctl[i], training_values[i]);
}
static u8 edp_link_status(const u8 *link_status, int r)
@@ -484,7 +471,7 @@ static int rk_edp_link_train_cr(struct rk_edp *edp)
u8 value;
value = DP_TRAINING_PATTERN_1;
- writel(value, &edp->regs->dp_training_ptn_set);
+ write32(&edp->regs->dp_training_ptn_set, value);
rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1);
memset(edp->train_set, 0, 4);
@@ -557,7 +544,7 @@ static int rk_edp_link_train_ce(struct rk_edp *edp)
u8 status[DP_LINK_STATUS_SIZE];
value = DP_TRAINING_PATTERN_2;
- writel(value, &edp->regs->dp_training_ptn_set);
+ write32(&edp->regs->dp_training_ptn_set, value);
rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1);
/* channel equalization loop */
@@ -635,18 +622,18 @@ static int rk_edp_hw_link_training(struct rk_edp *edp)
struct stopwatch sw;
/* Set link rate and count as you want to establish*/
- writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
- writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
+ write32(&edp->regs->link_bw_set, edp->link_train.link_rate);
+ write32(&edp->regs->lane_count_set, edp->link_train.lane_count);
if (rk_edp_link_train_cr(edp))
return -1;
if (rk_edp_link_train_ce(edp))
return -1;
- writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
+ write32(&edp->regs->dp_hw_link_training, HW_LT_EN);
stopwatch_init_msecs_expire(&sw, 10);
do {
- val = readl(&edp->regs->dp_hw_link_training);
+ val = read32(&edp->regs->dp_hw_link_training);
if (!(val & HW_LT_EN))
break;
} while (!stopwatch_expired(&sw));
@@ -668,12 +655,12 @@ static int rk_edp_select_i2c_device(struct rk_edp *edp,
/* Set EDID device address */
val = device_addr;
- writel(val, &edp->regs->aux_addr_7_0);
- writel(0x0, &edp->regs->aux_addr_15_8);
- writel(0x0, &edp->regs->aux_addr_19_16);
+ write32(&edp->regs->aux_addr_7_0, val);
+ write32(&edp->regs->aux_addr_15_8, 0x0);
+ write32(&edp->regs->aux_addr_19_16, 0x0);
/* Set offset from base address of EDID device */
- writel(val_addr, &edp->regs->buf_data[0]);
+ write32(&edp->regs->buf_data[0], val_addr);
/*
* Set I2C transaction and write address
@@ -682,7 +669,7 @@ static int rk_edp_select_i2c_device(struct rk_edp *edp,
*/
val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
AUX_TX_COMM_WRITE;
- writel(val, &edp->regs->aux_ch_ctl_1);
+ write32(&edp->regs->aux_ch_ctl_1, val);
/* Start AUX transaction */
retval = rk_edp_start_aux_transaction(edp);
@@ -708,7 +695,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp,
for (j = 0; j < 10; j++) { /* try 10 times */
/* Clear AUX CH data buffer */
val = BUF_CLR;
- writel(val, &edp->regs->buf_data_ctl);
+ write32(&edp->regs->buf_data_ctl, val);
/* Set normal AUX CH command */
clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY);
@@ -730,7 +717,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp,
*/
val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
AUX_TX_COMM_READ;
- writel(val, &edp->regs->aux_ch_ctl_1);
+ write32(&edp->regs->aux_ch_ctl_1, val);
/* Start AUX transaction */
retval = rk_edp_start_aux_transaction(edp);
@@ -742,7 +729,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp,
}
/* Check if Rx sends defer */
- val = readl(&edp->regs->aux_rx_comm);
+ val = read32(&edp->regs->aux_rx_comm);
if (val == AUX_RX_COMM_AUX_DEFER ||
val == AUX_RX_COMM_I2C_DEFER) {
edp_debug("Defer: %d\n\n", val);
@@ -754,7 +741,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp,
return -1;
for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
- val = readl(&edp->regs->buf_data[cur_data_idx]);
+ val = read32(&edp->regs->buf_data[cur_data_idx]);
edid[i + cur_data_idx] = (u8)val;
}
}
@@ -818,13 +805,13 @@ static void rk_edp_init_video(struct rk_edp *edp)
u32 val;
val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
- writel(val, &edp->regs->common_int_sta_1);
+ write32(&edp->regs->common_int_sta_1, val);
val = CHA_CRI(4) | CHA_CTRL;
- writel(val, &edp->regs->sys_ctl_2);
+ write32(&edp->regs->sys_ctl_2, val);
val = VID_HRES_TH(2) | VID_VRES_TH(0);
- writel(val, &edp->regs->video_ctl_8);
+ write32(&edp->regs->video_ctl_8, val);
}
static void rk_edp_config_video_slave_mode(struct rk_edp *edp)
@@ -843,24 +830,24 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp,
if (type == REGISTER_M) {
setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID);
val = m_value & 0xff;
- writel(val, &edp->regs->m_vid_0);
+ write32(&edp->regs->m_vid_0, val);
val = (m_value >> 8) & 0xff;
- writel(val, &edp->regs->m_vid_1);
+ write32(&edp->regs->m_vid_1, val);
val = (m_value >> 16) & 0xff;
- writel(val, &edp->regs->m_vid_2);
+ write32(&edp->regs->m_vid_2, val);
val = n_value & 0xff;
- writel(val, &edp->regs->n_vid_0);
+ write32(&edp->regs->n_vid_0, val);
val = (n_value >> 8) & 0xff;
- writel(val, &edp->regs->n_vid_1);
+ write32(&edp->regs->n_vid_1, val);
val = (n_value >> 16) & 0xff;
- writel(val, &edp->regs->n_vid_2);
+ write32(&edp->regs->n_vid_2, val);
} else {
clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID);
- writel(0x00, &edp->regs->n_vid_0);
- writel(0x80, &edp->regs->n_vid_1);
- writel(0x00, &edp->regs->n_vid_2);
+ write32(&edp->regs->n_vid_0, 0x00);
+ write32(&edp->regs->n_vid_1, 0x80);
+ write32(&edp->regs->n_vid_2, 0x00);
}
}
@@ -871,19 +858,19 @@ static int rk_edp_is_video_stream_clock_on(struct rk_edp *edp)
stopwatch_init_msecs_expire(&sw, 100);
do {
- val = readl(&edp->regs->sys_ctl_1);
+ val = read32(&edp->regs->sys_ctl_1);
/*must write value to update DET_STA bit status*/
- writel(val, &edp->regs->sys_ctl_1);
- val = readl(&edp->regs->sys_ctl_1);
+ write32(&edp->regs->sys_ctl_1, val);
+ val = read32(&edp->regs->sys_ctl_1);
if (!(val & DET_STA))
continue;
- val = readl(&edp->regs->sys_ctl_2);
+ val = read32(&edp->regs->sys_ctl_2);
/*must write value to update CHA_STA bit status*/
- writel(val, &edp->regs->sys_ctl_2);
- val = readl(&edp->regs->sys_ctl_2);
+ write32(&edp->regs->sys_ctl_2, val);
+ val = read32(&edp->regs->sys_ctl_2);
if (!(val & CHA_STA))
return 0;
} while (!stopwatch_expired(&sw));
@@ -898,12 +885,12 @@ static int rk_edp_is_video_stream_on(struct rk_edp *edp)
stopwatch_init_msecs_expire(&sw, 100);
do {
- val = readl(&edp->regs->sys_ctl_3);
+ val = read32(&edp->regs->sys_ctl_3);
/*must write value to update STRM_VALID bit status*/
- writel(val, &edp->regs->sys_ctl_3);
+ write32(&edp->regs->sys_ctl_3, val);
- val = readl(&edp->regs->sys_ctl_3);
+ val = read32(&edp->regs->sys_ctl_3);
if (!(val & STRM_VALID))
return 0;
} while (!stopwatch_expired(&sw));
@@ -942,16 +929,16 @@ static void rockchip_edp_force_hpd(struct rk_edp *edp)
{
u32 val;
- val = readl(&edp->regs->sys_ctl_3);
+ val = read32(&edp->regs->sys_ctl_3);
val |= (F_HPD | HPD_CTRL);
- writel(val, &edp->regs->sys_ctl_3);
+ write32(&edp->regs->sys_ctl_3, val);
}
static int rockchip_edp_get_plug_in_status(struct rk_edp *edp)
{
u32 val;
- val = readl(&edp->regs->sys_ctl_3);
+ val = read32(&edp->regs->sys_ctl_3);
if (val & HPD_STATUS)
return 1;
@@ -1020,11 +1007,11 @@ void rk_edp_init(u32 vop_id)
rk_edp.regs = (struct rk3288_edp_regs *)EDP_BASE;
/* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
- writel(RK_SETBITS(1 << 4), &rk3288_grf->soc_con12);
+ write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4));
/* select epd signal from vop0 or vop1 */
val = (vop_id == 1) ? RK_SETBITS(1 << 5) : RK_CLRBITS(1 << 5);
- writel(val, &rk3288_grf->soc_con6);
+ write32(&rk3288_grf->soc_con6, val);
rockchip_edp_wait_hpd(&rk_edp);
diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c
index b84d6a0821..5fc9c7b185 100644
--- a/src/soc/rockchip/rk3288/gpio.c
+++ b/src/soc/rockchip/rk3288/gpio.c
@@ -52,9 +52,8 @@ static void __gpio_input(gpio_t gpio, u32 pull)
clrsetbits_le32(&rk3288_pmu->gpio0pull[gpio.bank],
3 << (gpio.idx * 2), pull << (gpio.idx * 2));
else
- writel(RK_CLRSETBITS(3 << (gpio.idx * 2),
- pull << (gpio.idx * 2)),
- &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]);
+ write32(&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank],
+ RK_CLRSETBITS(3 << (gpio.idx * 2), pull << (gpio.idx * 2)));
}
void gpio_input(gpio_t gpio)
@@ -74,7 +73,7 @@ void gpio_input_pullup(gpio_t gpio)
int gpio_get(gpio_t gpio)
{
- return (readl(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
+ return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
}
void gpio_output(gpio_t gpio, int value)
diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c
index d69bb7cb78..6174aafd3c 100644
--- a/src/soc/rockchip/rk3288/i2c.c
+++ b/src/soc/rockchip/rk3288/i2c.c
@@ -97,10 +97,10 @@ static int i2c_send_start(struct rk3288_i2c_regs *reg_addr)
int timeout = I2C_TIMEOUT_US;
i2c_info("I2c Start::Send Start bit\n");
- writel(I2C_CLEANI, &reg_addr->i2c_ipd);
- writel(I2C_EN | I2C_START, &reg_addr->i2c_con);
+ write32(&reg_addr->i2c_ipd, I2C_CLEANI);
+ write32(&reg_addr->i2c_con, I2C_EN | I2C_START);
while (timeout--) {
- if (readl(&reg_addr->i2c_ipd) & I2C_STARTI)
+ if (read32(&reg_addr->i2c_ipd) & I2C_STARTI)
break;
udelay(1);
}
@@ -119,14 +119,14 @@ static int i2c_send_stop(struct rk3288_i2c_regs *reg_addr)
int timeout = I2C_TIMEOUT_US;
i2c_info("I2c Stop::Send Stop bit\n");
- writel(I2C_CLEANI, &reg_addr->i2c_ipd);
- writel(I2C_EN | I2C_STOP, &reg_addr->i2c_con);
+ write32(&reg_addr->i2c_ipd, I2C_CLEANI);
+ write32(&reg_addr->i2c_con, I2C_EN | I2C_STOP);
while (timeout--) {
- if (readl(&reg_addr->i2c_ipd) & I2C_STOPI)
+ if (read32(&reg_addr->i2c_ipd) & I2C_STOPI)
break;
udelay(1);
}
- writel(0, &reg_addr->i2c_con);
+ write32(&reg_addr->i2c_con, 0);
if (timeout <= 0) {
printk(BIOS_ERR, "I2C Stop::Send Stop Bit Timeout\n");
res = I2C_TIMEOUT;
@@ -147,8 +147,8 @@ static int i2c_read(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment)
unsigned int con = 0;
unsigned int i, j;
- writel(I2C_8BIT | segment.chip << 1 | 1, &reg_addr->i2c_mrxaddr);
- writel(0, &reg_addr->i2c_mrxraddr);
+ write32(&reg_addr->i2c_mrxaddr, I2C_8BIT | segment.chip << 1 | 1);
+ write32(&reg_addr->i2c_mrxraddr, 0);
con = I2C_MODE_TRX | I2C_EN | I2C_ACT2NAK;
while (bytes_remaining) {
bytes_transfered = MIN(bytes_remaining, 32);
@@ -157,30 +157,30 @@ static int i2c_read(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment)
con |= I2C_EN | I2C_NAK;
words_transfered = ALIGN_UP(bytes_transfered, 4) / 4;
- writel(I2C_CLEANI, &reg_addr->i2c_ipd);
- writel(con, &reg_addr->i2c_con);
- writel(bytes_transfered, &reg_addr->i2c_mrxcnt);
+ write32(&reg_addr->i2c_ipd, I2C_CLEANI);
+ write32(&reg_addr->i2c_con, con);
+ write32(&reg_addr->i2c_mrxcnt, bytes_transfered);
timeout = I2C_TIMEOUT_US;
while (timeout--) {
- if (readl(&reg_addr->i2c_ipd) & I2C_NAKRCVI) {
- writel(0, &reg_addr->i2c_mrxcnt);
- writel(0, &reg_addr->i2c_con);
+ if (read32(&reg_addr->i2c_ipd) & I2C_NAKRCVI) {
+ write32(&reg_addr->i2c_mrxcnt, 0);
+ write32(&reg_addr->i2c_con, 0);
return I2C_NOACK;
}
- if (readl(&reg_addr->i2c_ipd) & I2C_MBRFI)
+ if (read32(&reg_addr->i2c_ipd) & I2C_MBRFI)
break;
udelay(1);
}
if (timeout <= 0) {
printk(BIOS_ERR, "I2C Read::Recv Data Timeout\n");
- writel(0, &reg_addr->i2c_mrxcnt);
- writel(0, &reg_addr->i2c_con);
+ write32(&reg_addr->i2c_mrxcnt, 0);
+ write32(&reg_addr->i2c_con, 0);
return I2C_TIMEOUT;
}
for (i = 0; i < words_transfered; i++) {
- rxdata = readl(&reg_addr->rxdata[i]);
+ rxdata = read32(&reg_addr->rxdata[i]);
i2c_info("I2c Read::RXDATA[%d] = 0x%x\n", i, rxdata);
for (j = 0; j < 4; j++) {
if ((i * 4 + j) == bytes_transfered)
@@ -215,32 +215,33 @@ static int i2c_write(struct rk3288_i2c_regs *reg_addr, struct i2c_seg segment)
break;
txdata |= (*data++) << (j * 8);
} while (++j < 4);
- writel(txdata, &reg_addr->txdata[i]);
+ write32(&reg_addr->txdata[i], txdata);
j = 0;
i2c_info("I2c Write::TXDATA[%d] = 0x%x\n", i, txdata);
txdata = 0;
}
- writel(I2C_CLEANI, &reg_addr->i2c_ipd);
- writel(I2C_EN | I2C_MODE_TX | I2C_ACT2NAK, &reg_addr->i2c_con);
- writel(bytes_transfered, &reg_addr->i2c_mtxcnt);
+ write32(&reg_addr->i2c_ipd, I2C_CLEANI);
+ write32(&reg_addr->i2c_con,
+ I2C_EN | I2C_MODE_TX | I2C_ACT2NAK);
+ write32(&reg_addr->i2c_mtxcnt, bytes_transfered);
timeout = I2C_TIMEOUT_US;
while (timeout--) {
- if (readl(&reg_addr->i2c_ipd) & I2C_NAKRCVI) {
- writel(0, &reg_addr->i2c_mtxcnt);
- writel(0, &reg_addr->i2c_con);
+ if (read32(&reg_addr->i2c_ipd) & I2C_NAKRCVI) {
+ write32(&reg_addr->i2c_mtxcnt, 0);
+ write32(&reg_addr->i2c_con, 0);
return I2C_NOACK;
}
- if (readl(&reg_addr->i2c_ipd) & I2C_MBTFI)
+ if (read32(&reg_addr->i2c_ipd) & I2C_MBTFI)
break;
udelay(1);
}
if (timeout <= 0) {
printk(BIOS_ERR, "I2C Write::Send Data Timeout\n");
- writel(0, &reg_addr->i2c_mtxcnt);
- writel(0, &reg_addr->i2c_con);
+ write32(&reg_addr->i2c_mtxcnt, 0);
+ write32(&reg_addr->i2c_con, 0);
return I2C_TIMEOUT;
}
@@ -310,5 +311,5 @@ void i2c_init(unsigned int bus, unsigned int hz)
divh = clk_div * 3 / 7 - 1;
divl = clk_div - divh - 2;
assert((divh < 65536) && (divl < 65536));
- writel((divh << 16) | (divl << 0), &regs->i2c_clkdiv);
+ write32(&regs->i2c_clkdiv, (divh << 16) | (divl << 0));
}
diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c
index a44724959e..fb47dc8312 100644
--- a/src/soc/rockchip/rk3288/pwm.c
+++ b/src/soc/rockchip/rk3288/pwm.c
@@ -73,17 +73,15 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
unsigned long period, duty;
/*use rk pwm*/
- writel(RK_SETBITS(1 << 0), &rk3288_grf->soc_con2);
+ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
- writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
- PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
- RK_PWM_DISABLE,
- &rk3288_pwm->pwm[id].pwm_ctrl);
+ write32(&rk3288_pwm->pwm[id].pwm_ctrl,
+ PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
- writel(period, &rk3288_pwm->pwm[id].pwm_period_hpr);
- writel(duty, &rk3288_pwm->pwm[id].pwm_duty_lpr);
+ write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period);
+ write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty);
setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
}
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index 44f9172bee..86acf6dc3f 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -515,7 +515,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
for (i = 0; i < n / sizeof(u32); i++) {
- writel(*src, dest);
+ write32(dest, *src);
src++;
dest++;
}
@@ -571,27 +571,27 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs,
static void dfi_cfg(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 dramtype)
{
- writel(DFI_INIT_START, &ddr_pctl_regs->dfistcfg0);
- writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
- &ddr_pctl_regs->dfistcfg1);
- writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &ddr_pctl_regs->dfistcfg2);
- writel(TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN,
- &ddr_pctl_regs->dfilpcfg0);
-
- writel(TCTRL_DELAY_TIME(2), &ddr_pctl_regs->dfitctrldelay);
- writel(TPHY_WRDATA_TIME(1), &ddr_pctl_regs->dfitphywrdata);
- writel(TPHY_RDLAT_TIME(0xf), &ddr_pctl_regs->dfitphyrdlat);
- writel(TDRAM_CLK_DIS_TIME(2), &ddr_pctl_regs->dfitdramclkdis);
- writel(TDRAM_CLK_EN_TIME(2), &ddr_pctl_regs->dfitdramclken);
- writel(0x1, &ddr_pctl_regs->dfitphyupdtype0);
+ write32(&ddr_pctl_regs->dfistcfg0, DFI_INIT_START);
+ write32(&ddr_pctl_regs->dfistcfg1,
+ DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN);
+ write32(&ddr_pctl_regs->dfistcfg2, DFI_PARITY_INTR_EN | DFI_PARITY_EN);
+ write32(&ddr_pctl_regs->dfilpcfg0,
+ TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN);
+
+ write32(&ddr_pctl_regs->dfitctrldelay, TCTRL_DELAY_TIME(2));
+ write32(&ddr_pctl_regs->dfitphywrdata, TPHY_WRDATA_TIME(1));
+ write32(&ddr_pctl_regs->dfitphyrdlat, TPHY_RDLAT_TIME(0xf));
+ write32(&ddr_pctl_regs->dfitdramclkdis, TDRAM_CLK_DIS_TIME(2));
+ write32(&ddr_pctl_regs->dfitdramclken, TDRAM_CLK_EN_TIME(2));
+ write32(&ddr_pctl_regs->dfitphyupdtype0, 0x1);
/* cs0 and cs1 write odt enable */
- writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
- &ddr_pctl_regs->dfiodtcfg);
+ write32(&ddr_pctl_regs->dfiodtcfg,
+ (RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL));
/* odt write length */
- writel(ODT_LEN_BL8_W(7), &ddr_pctl_regs->dfiodtcfg1);
+ write32(&ddr_pctl_regs->dfiodtcfg1, ODT_LEN_BL8_W(7));
/* phyupd and ctrlupd disabled */
- writel(0, &ddr_pctl_regs->dfiupdcfg);
+ write32(&ddr_pctl_regs->dfiupdcfg, 0);
}
static void pctl_cfg(u32 channel,
@@ -605,39 +605,33 @@ static void pctl_cfg(u32 channel,
sizeof(sdram_params->pctl_timing));
switch (sdram_params->dramtype) {
case LPDDR3:
- writel(sdram_params->pctl_timing.tcl - 1,
- &ddr_pctl_regs->dfitrddataen);
- writel(sdram_params->pctl_timing.tcwl,
- &ddr_pctl_regs->dfitphywrlat);
- writel(LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN
- | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST
- | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg);
- writel(MSCH_MAINDDR3(channel, 0), &rk3288_grf->soc_con0);
-
- writel(PUBL_LPDDR3_EN(channel, 1)
- | PCTL_BST_DISABLE(channel, 1)
- | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt),
- &rk3288_grf->soc_con2);
+ write32(&ddr_pctl_regs->dfitrddataen,
+ sdram_params->pctl_timing.tcl - 1);
+ write32(&ddr_pctl_regs->dfitphywrlat,
+ sdram_params->pctl_timing.tcwl);
+ write32(&ddr_pctl_regs->mcfg,
+ LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0));
+ write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 0));
+
+ write32(&rk3288_grf->soc_con2,
+ PUBL_LPDDR3_EN(channel, 1) | PCTL_BST_DISABLE(channel, 1) | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt));
break;
case DDR3:
if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE)
- writel(sdram_params->pctl_timing.tcl - 3,
- &ddr_pctl_regs->dfitrddataen);
+ write32(&ddr_pctl_regs->dfitrddataen,
+ sdram_params->pctl_timing.tcl - 3);
else
- writel(sdram_params->pctl_timing.tcl - 2,
- &ddr_pctl_regs->dfitrddataen);
- writel(sdram_params->pctl_timing.tcwl - 1,
- &ddr_pctl_regs->dfitphywrlat);
- writel(MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN
- | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW
- | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg);
- writel(MSCH_MAINDDR3(channel, 1), &rk3288_grf->soc_con0);
-
- writel(PUBL_LPDDR3_EN(channel, 0)
- | PCTL_BST_DISABLE(channel, 0)
- | PCTL_LPDDR3_ODT_EN(channel, 0),
- &rk3288_grf->soc_con2);
+ write32(&ddr_pctl_regs->dfitrddataen,
+ sdram_params->pctl_timing.tcl - 2);
+ write32(&ddr_pctl_regs->dfitphywrlat,
+ sdram_params->pctl_timing.tcwl - 1);
+ write32(&ddr_pctl_regs->mcfg,
+ MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0));
+ write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 1));
+
+ write32(&rk3288_grf->soc_con2,
+ PUBL_LPDDR3_EN(channel, 0) | PCTL_BST_DISABLE(channel, 0) | PCTL_LPDDR3_ODT_EN(channel, 0));
break;
}
@@ -656,23 +650,17 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
copy_to_reg(&ddr_publ_regs->dtpr[0],
&(sdram_params->phy_timing.dtpr0),
sizeof(sdram_params->phy_timing));
- writel(sdram_params->noc_timing, &msch_regs->ddrtiming);
- writel(0x3f, &msch_regs->readlatency);
- writel(sdram_params->noc_activate, &msch_regs->activate);
- writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1),
- &msch_regs->devtodev);
- writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz
- * 5120, 1000))
- | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz
- * 50, 1000))
- | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]);
- writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz
- * 500000, 1000))
- | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz
- * 400, 1000)), &ddr_publ_regs->ptr[1]);
- writel(PRT_DINIT2(MIN(dinit2, 0x1ffff))
- | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz
- * 1000, 1000)), &ddr_publ_regs->ptr[2]);
+ write32(&msch_regs->ddrtiming, sdram_params->noc_timing);
+ write32(&msch_regs->readlatency, 0x3f);
+ write32(&msch_regs->activate, sdram_params->noc_activate);
+ write32(&msch_regs->devtodev,
+ BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1));
+ write32(&ddr_publ_regs->ptr[0],
+ PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000)) | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000)) | PRT_ITMSRST(8));
+ write32(&ddr_publ_regs->ptr[1],
+ PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000)));
+ write32(&ddr_publ_regs->ptr[2],
+ PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000)));
switch (sdram_params->dramtype) {
case LPDDR3:
@@ -683,8 +671,8 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
DDRMD_CFG(DDRMD_LPDDR2_LPDDR3));
clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK,
DQSRES_CFG(4) | DQSNRES_CFG(0xc));
- i = TDQSCKMAX_VAL(readl(&ddr_publ_regs->dtpr[1]))
- - TDQSCK_VAL(readl(&ddr_publ_regs->dtpr[1]));
+ i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1]))
+ - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1]));
clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK,
DQSGE_CFG(i) | DQSGX_CFG(i));
break;
@@ -713,7 +701,7 @@ static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs)
setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST
| PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
udelay(1);
- while ((readl(&ddr_publ_regs->pgsr) &
+ while ((read32(&ddr_publ_regs->pgsr) &
(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
;
@@ -722,9 +710,9 @@ static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs)
static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
u32 cmd, u32 arg)
{
- writel((START_CMD | (rank << 20) | arg | cmd), &ddr_pctl_regs->mcmd);
+ write32(&ddr_pctl_regs->mcmd, (START_CMD | (rank << 20) | arg | cmd));
udelay(1);
- while (readl(&ddr_pctl_regs->mcmd) & START_CMD)
+ while (read32(&ddr_pctl_regs->mcmd) & START_CMD)
;
}
@@ -736,7 +724,7 @@ static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs,
| PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
| (dramtype == DDR3 ? PIR_DRAMRST : 0)));
udelay(1);
- while ((readl(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
+ while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
!= (PGSR_IDONE | PGSR_DLDONE))
;
}
@@ -747,16 +735,16 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs,
unsigned int state;
while (1) {
- state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
+ state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
switch (state) {
case LOW_POWER:
- writel(WAKEUP_STATE, &ddr_pctl_regs->sctl);
- while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
+ write32(&ddr_pctl_regs->sctl, WAKEUP_STATE);
+ while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
!= ACCESS)
;
/* wait DLL lock */
- while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
+ while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
!= PGSR_DLDONE)
;
/* if at low power state,need wakeup first,
@@ -765,8 +753,8 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs,
*/
case ACCESS:
case INIT_MEM:
- writel(CFG_STATE, &ddr_pctl_regs->sctl);
- while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
+ write32(&ddr_pctl_regs->sctl, CFG_STATE);
+ while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
!= CONFIG)
;
break;
@@ -786,8 +774,7 @@ static void set_bandwidth_ratio(u32 channel, u32 n)
if (n == 1) {
setbits_le32(&ddr_pctl_regs->ppcfg, 1);
- writel(RK_SETBITS(1 << (8 + channel)),
- &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel)));
setbits_le32(&msch_regs->ddrtiming, 1 << 31);
/* Data Byte disable*/
clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1);
@@ -799,8 +786,7 @@ static void set_bandwidth_ratio(u32 channel, u32 n)
DXDLLCR_DLLDIS);
} else {
clrbits_le32(&ddr_pctl_regs->ppcfg, 1);
- writel(RK_CLRBITS(1 << (8 + channel)),
- &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel)));
clrbits_le32(&msch_regs->ddrtiming, 1 << 31);
/* Data Byte enable*/
setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1);
@@ -838,7 +824,7 @@ static int data_training(u32 channel,
struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel];
/* disable auto refresh */
- writel(0, &ddr_pctl_regs->trefi);
+ write32(&ddr_pctl_regs->trefi, 0);
if (sdram_params->dramtype != LPDDR3)
setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1));
@@ -856,21 +842,21 @@ static int data_training(u32 channel,
PIR_CLRSR);
udelay(1);
/* wait echo byte DTDONE */
- while ((readl(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank)
+ while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank)
!= rank)
;
- while ((readl(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank)
+ while ((read32(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank)
!= rank)
;
- if (!(readl(&ddr_pctl_regs->ppcfg) & 1)) {
- while ((readl(&ddr_publ_regs->datx8[2].dxgsr[0])
+ if (!(read32(&ddr_pctl_regs->ppcfg) & 1)) {
+ while ((read32(&ddr_publ_regs->datx8[2].dxgsr[0])
& rank) != rank)
;
- while ((readl(&ddr_publ_regs->datx8[3].dxgsr[0])
+ while ((read32(&ddr_publ_regs->datx8[3].dxgsr[0])
& rank) != rank)
;
}
- if (readl(&ddr_publ_regs->pgsr) &
+ if (read32(&ddr_publ_regs->pgsr) &
(PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
ret = -1;
break;
@@ -884,7 +870,7 @@ static int data_training(u32 channel,
clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1));
/* resume auto refresh */
- writel(sdram_params->pctl_timing.trefi, &ddr_pctl_regs->trefi);
+ write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi);
return ret;
}
@@ -897,30 +883,30 @@ static void move_to_access_state(u32 chnum)
unsigned int state;
while (1) {
- state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
+ state = read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK;
switch (state) {
case LOW_POWER:
- if (LP_TRIG_VAL(readl(&ddr_pctl_regs->stat)) == 1)
+ if (LP_TRIG_VAL(read32(&ddr_pctl_regs->stat)) == 1)
return;
- writel(WAKEUP_STATE, &ddr_pctl_regs->sctl);
- while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
+ write32(&ddr_pctl_regs->sctl, WAKEUP_STATE);
+ while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
!= ACCESS)
;
/* wait DLL lock */
- while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
+ while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE)
!= PGSR_DLDONE)
;
break;
case INIT_MEM:
- writel(CFG_STATE, &ddr_pctl_regs->sctl);
- while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
+ write32(&ddr_pctl_regs->sctl, CFG_STATE);
+ while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
!= CONFIG)
;
case CONFIG:
- writel(GO_STATE, &ddr_pctl_regs->sctl);
- while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
+ write32(&ddr_pctl_regs->sctl, GO_STATE);
+ while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK)
== CONFIG)
;
break;
@@ -943,7 +929,7 @@ static void dram_cfg_rbc(u32 chnum,
else
clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK);
- writel(sdram_params->ddrconfig, &msch_regs->ddrconf);
+ write32(&msch_regs->ddrconf, sdram_params->ddrconfig);
}
static void dram_all_config(const struct rk3288_sdram_params *sdram_params)
@@ -968,9 +954,9 @@ static void dram_all_config(const struct rk3288_sdram_params *sdram_params)
dram_cfg_rbc(channel, sdram_params);
}
- writel(sys_reg, &rk3288_pmu->sys_reg[2]);
- writel(RK_CLRSETBITS(0x1F, sdram_params->stride),
- &rk3288_sgrf->soc_con2);
+ write32(&rk3288_pmu->sys_reg[2], sys_reg);
+ write32(&rk3288_sgrf->soc_con2,
+ RK_CLRSETBITS(0x1F, sdram_params->stride));
}
void sdram_init(const struct rk3288_sdram_params *sdram_params)
@@ -1007,8 +993,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
phy_init(ddr_publ_regs);
- writel(POWER_UP_START, &ddr_pctl_regs->powctl);
- while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE))
+ write32(&ddr_pctl_regs->powctl, POWER_UP_START);
+ while (!(read32(&ddr_pctl_regs->powstat) & POWER_UP_DONE))
;
memory_init(ddr_publ_regs, sdram_params->dramtype);
@@ -1045,8 +1031,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
/* DS=40ohm,ODT=155ohm */
zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2)
| PU_OUTPUT(0x19) | PD_OUTPUT(0x19);
- writel(zqcr, &ddr_publ_regs->zq1cr[0]);
- writel(zqcr, &ddr_publ_regs->zq0cr[0]);
+ write32(&ddr_publ_regs->zq1cr[0], zqcr);
+ write32(&ddr_publ_regs->zq0cr[0], zqcr);
if (sdram_params->dramtype == LPDDR3) {
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
@@ -1056,11 +1042,11 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
MRS_CMD, LPDDR2_MA(11) |
sdram_params->odt ? LPDDR2_OP(3) : 0);
if (channel == 0) {
- writel(0, &ddr_pctl_regs->mrrcfg0);
+ write32(&ddr_pctl_regs->mrrcfg0, 0);
send_command(ddr_pctl_regs, 1, MRR_CMD,
LPDDR2_MA(0x8));
/* S8 */
- if ((readl(&ddr_pctl_regs->mrrstat0) & 0x3)
+ if ((read32(&ddr_pctl_regs->mrrstat0) & 0x3)
!= 3)
die("SDRAM initialization failed!");
}
@@ -1078,7 +1064,7 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
if (sdram_params->dramtype == LPDDR3) {
u32 i;
- writel(0, &ddr_pctl_regs->mrrcfg0);
+ write32(&ddr_pctl_regs->mrrcfg0, 0);
for (i = 0; i < 17; i++)
send_command(ddr_pctl_regs, 1, MRR_CMD,
LPDDR2_MA(i));
@@ -1098,7 +1084,7 @@ size_t sdram_size_mb(void)
if (!size_mb) {
- u32 sys_reg = readl(&rk3288_pmu->sys_reg[2]);
+ u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]);
u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);
for (ch = 0; ch < ch_num; ch++) {
diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c
index a71fcd16bf..2df0a2857a 100644
--- a/src/soc/rockchip/rk3288/software_i2c.c
+++ b/src/soc/rockchip/rk3288/software_i2c.c
@@ -81,20 +81,20 @@ void software_i2c_attach(unsigned bus)
clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
break;
case 1:
- writel(IOMUX_GPIO(IOMUX_I2C1), &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1));
break;
case 2:
- writel(IOMUX_GPIO(IOMUX_I2C2), &rk3288_grf->iomux_i2c2);
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_GPIO(IOMUX_I2C2));
break;
case 3:
- writel(IOMUX_GPIO(IOMUX_I2C3), &rk3288_grf->iomux_i2c3);
+ write32(&rk3288_grf->iomux_i2c3, IOMUX_GPIO(IOMUX_I2C3));
break;
case 4:
- writel(IOMUX_GPIO(IOMUX_I2C4), &rk3288_grf->iomux_i2c4);
+ write32(&rk3288_grf->iomux_i2c4, IOMUX_GPIO(IOMUX_I2C4));
break;
case 5:
- writel(IOMUX_GPIO(IOMUX_I2C5SCL), &rk3288_grf->iomux_i2c5scl);
- writel(IOMUX_GPIO(IOMUX_I2C5SDA), &rk3288_grf->iomux_i2c5sda);
+ write32(&rk3288_grf->iomux_i2c5scl, IOMUX_GPIO(IOMUX_I2C5SCL));
+ write32(&rk3288_grf->iomux_i2c5sda, IOMUX_GPIO(IOMUX_I2C5SDA));
break;
default:
die("Unknown I2C bus number!");
@@ -116,20 +116,20 @@ void software_i2c_detach(unsigned bus)
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
break;
case 1:
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
break;
case 2:
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);
break;
case 3:
- writel(IOMUX_I2C3, &rk3288_grf->iomux_i2c3);
+ write32(&rk3288_grf->iomux_i2c3, IOMUX_I2C3);
break;
case 4:
- writel(IOMUX_I2C4, &rk3288_grf->iomux_i2c4);
+ write32(&rk3288_grf->iomux_i2c4, IOMUX_I2C4);
break;
case 5:
- writel(IOMUX_I2C5SCL, &rk3288_grf->iomux_i2c5scl);
- writel(IOMUX_I2C5SDA, &rk3288_grf->iomux_i2c5sda);
+ write32(&rk3288_grf->iomux_i2c5scl, IOMUX_I2C5SCL);
+ write32(&rk3288_grf->iomux_i2c5sda, IOMUX_I2C5SDA);
break;
default:
die("Unknown I2C bus number!");
diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c
index fe4e377a08..aa70f3e0e5 100644
--- a/src/soc/rockchip/rk3288/spi.c
+++ b/src/soc/rockchip/rk3288/spi.c
@@ -87,9 +87,9 @@ static void spi_cs_deactivate(struct spi_slave *slave)
static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable)
{
if (enable == 1)
- writel(1, &regs->spienr);
+ write32(&regs->spienr, 1);
else
- writel(0, &regs->spienr);
+ write32(&regs->spienr, 0);
}
static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
@@ -100,7 +100,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
clk_div = SPI_SRCCLK_HZ / hz;
clk_div = (clk_div + 1) & 0xfffe;
assert((clk_div - 1) * hz == SPI_SRCCLK_HZ);
- writel(clk_div, &regs->baudr);
+ write32(&regs->baudr, clk_div);
}
void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
@@ -139,11 +139,11 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
/* Frame Format */
ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET);
- writel(ctrlr0, &regs->ctrlr0);
+ write32(&regs->ctrlr0, ctrlr0);
/* fifo depth */
- writel(SPI_FIFO_DEPTH / 2 - 1, &regs->txftlr);
- writel(SPI_FIFO_DEPTH / 2 - 1, &regs->rxftlr);
+ write32(&regs->txftlr, SPI_FIFO_DEPTH / 2 - 1);
+ write32(&regs->rxftlr, SPI_FIFO_DEPTH / 2 - 1);
}
int spi_claim_bus(struct spi_slave *slave)
@@ -163,7 +163,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs)
stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_US);
do {
- if (!(readl(&regs->sr) & SR_BUSY))
+ if (!(read32(&regs->sr) & SR_BUSY))
return 0;
} while (!stopwatch_expired(&sw));
printk(BIOS_DEBUG,
@@ -207,18 +207,18 @@ static int do_xfer(struct spi_slave *slave, const void *dout,
min_xfer = MIN(*bytes_in, *bytes_out);
while (min_xfer) {
- uint32_t sr = readl(&regs->sr);
+ uint32_t sr = read32(&regs->sr);
int xferred = 0; /* in either (or both) directions */
if (*bytes_out && !(sr & SR_TF_FULL)) {
- writel(*out_buf, &regs->txdr);
+ write32(&regs->txdr, *out_buf);
out_buf++;
*bytes_out -= 1;
xferred = 1;
}
if (*bytes_in && !(sr & SR_RF_EMPT)) {
- *in_buf = readl(&regs->rxdr) & 0xff;
+ *in_buf = read32(&regs->rxdr) & 0xff;
in_buf++;
*bytes_in -= 1;
xferred = 1;
@@ -266,7 +266,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
set_transfer_mode(regs, bytes_out, bytes_in);
/* MAX() in case either counter is 0 */
- writel(MAX(in_now, out_now) - 1, &regs->ctrlr1);
+ write32(&regs->ctrlr1, MAX(in_now, out_now) - 1);
rockchip_spi_enable_chip(regs, 1);
diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c
index d373f7a39c..07be49bfe9 100644
--- a/src/soc/rockchip/rk3288/timer.c
+++ b/src/soc/rockchip/rk3288/timer.c
@@ -41,7 +41,7 @@ void timer_monotonic_get(struct mono_time *mt)
void init_timer(void)
{
- writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0);
- writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1);
- writel(1, &timer7_ptr->timer_ctrl_reg);
+ write32(&timer7_ptr->timer_load_count0, TIMER_LOAD_VAL);
+ write32(&timer7_ptr->timer_load_count1, TIMER_LOAD_VAL);
+ write32(&timer7_ptr->timer_ctrl_reg, 1);
}
diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c
index a2d6ec499a..cada767889 100644
--- a/src/soc/rockchip/rk3288/tsadc.c
+++ b/src/soc/rockchip/rk3288/tsadc.c
@@ -94,13 +94,13 @@ void tsadc_init(void)
TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 |
TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1);
- writel(AUTO_PERIOD, &rk3288_tsadc->auto_period);
- writel(AUTO_DEBOUNCE, &rk3288_tsadc->hight_int_debounce);
- writel(AUTO_PERIOD_HT, &rk3288_tsadc->auto_period_ht);
- writel(AUTO_DEBOUNCE_HT, &rk3288_tsadc->hight_tshut_debounce);
+ write32(&rk3288_tsadc->auto_period, AUTO_PERIOD);
+ write32(&rk3288_tsadc->hight_int_debounce, AUTO_DEBOUNCE);
+ write32(&rk3288_tsadc->auto_period_ht, AUTO_PERIOD_HT);
+ write32(&rk3288_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT);
- writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp1_shut);
- writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp2_shut);
+ write32(&rk3288_tsadc->comp1_shut, TSADC_SHUT_VALUE);
+ write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE);
/* polarity set to high,channel1 for cpu,channel2 for gpu */
setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN |
diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
index 7685ff9a41..8ba1fdee73 100644
--- a/src/soc/rockchip/rk3288/uart.c
+++ b/src/soc/rockchip/rk3288/uart.c
@@ -92,43 +92,42 @@ static void rk3288_uart_init(void)
rk3288_uart_tx_flush();
// Disable interrupts.
- writel(0, &uart_ptr->ier);
+ write32(&uart_ptr->ier, 0);
// Force DTR and RTS to high.
- writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+ write32(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
// Set line configuration, access divisor latches.
- writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ write32(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
// Set the divisor.
- writel(divisor & 0xff, &uart_ptr->dll);
- writel((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ write32(&uart_ptr->dll, divisor & 0xff);
+ write32(&uart_ptr->dlm, (divisor >> 8) & 0xff);
// Hide the divisor latches.
- writel(line_config, &uart_ptr->lcr);
+ write32(&uart_ptr->lcr, line_config);
// Enable FIFOs, and clear receive and transmit.
- writel(UART8250_FCR_FIFO_EN |
- UART8250_FCR_CLEAR_RCVR |
- UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+ write32(&uart_ptr->fcr,
+ UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT);
}
static void rk3288_uart_tx_byte(unsigned char data)
{
- while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE));
- writel(data, &uart_ptr->thr);
+ while (!(read32(&uart_ptr->lsr) & UART8250_LSR_THRE));
+ write32(&uart_ptr->thr, data);
}
static void rk3288_uart_tx_flush(void)
{
- while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+ while (!(read32(&uart_ptr->lsr) & UART8250_LSR_TEMT));
}
static unsigned char rk3288_uart_rx_byte(void)
{
if (!rk3288_uart_tst_byte())
return 0;
- return readl(&uart_ptr->rbr);
+ return read32(&uart_ptr->rbr);
}
static int rk3288_uart_tst_byte(void)
{
- return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
+ return (read32(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
}
diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c
index 378e6b8e90..915d452d4b 100644
--- a/src/soc/rockchip/rk3288/vop.c
+++ b/src/soc/rockchip/rk3288/vop.c
@@ -48,16 +48,14 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
u32 xpos = 0, ypos = 0;
struct rk3288_vop_regs *preg = vop_regs[vop_id];
- writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
- &preg->win0_act_info);
+ write32(&preg->win0_act_info,
+ V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
- writel(V_DSP_XST(xpos + hsync_len + hback_porch) |
- V_DSP_YST(ypos + vsync_len + vback_porch),
- &preg->win0_dsp_st);
+ write32(&preg->win0_dsp_st,
+ V_DSP_XST(xpos + hsync_len + hback_porch) | V_DSP_YST(ypos + vsync_len + vback_porch));
- writel(V_DSP_WIDTH(hactive - 1) |
- V_DSP_HEIGHT(vactive - 1),
- &preg->win0_dsp_info);
+ write32(&preg->win0_dsp_info,
+ V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1));
clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
V_WIN0_KEY_EN(0) |
@@ -66,19 +64,16 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
switch (edid->framebuffer_bits_per_pixel) {
case 16:
rgb_mode = RGB565;
- writel(V_RGB565_VIRWIDTH(hactive),
- &preg->win0_vir);
+ write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive));
break;
case 24:
rgb_mode = RGB888;
- writel(V_RGB888_VIRWIDTH(hactive),
- &preg->win0_vir);
+ write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive));
break;
case 32:
default:
rgb_mode = ARGB8888;
- writel(V_ARGB888_VIRWIDTH(hactive),
- &preg->win0_vir);
+ write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive));
break;
}
@@ -96,9 +91,9 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
V_WIN0_LB_MODE(lb_mode) |
V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
- writel(fbbase, &preg->win0_yrgb_mst);
+ write32(&preg->win0_yrgb_mst, fbbase);
- writel(0x01, &preg->reg_cfg_done); /* enable reg config */
+ write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
}
void rkvop_mode_set(u32 vop_id, const struct edid *edid)
@@ -116,29 +111,23 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid)
clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1));
clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE,
V_DSP_OUT_MODE(15));
- writel(V_HSYNC(hsync_len) |
- V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
- &preg->dsp_htotal_hs_end);
+ write32(&preg->dsp_htotal_hs_end,
+ V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
- writel(V_HEAP(hsync_len + hback_porch + hactive) |
- V_HASP(hsync_len + hback_porch),
- &preg->dsp_hact_st_end);
+ write32(&preg->dsp_hact_st_end,
+ V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch));
- writel(V_VSYNC(vsync_len) |
- V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
- &preg->dsp_vtotal_vs_end);
+ write32(&preg->dsp_vtotal_vs_end,
+ V_VSYNC(vsync_len) | V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch));
- writel(V_VAEP(vsync_len + vback_porch + vactive)|
- V_VASP(vsync_len + vback_porch),
- &preg->dsp_vact_st_end);
+ write32(&preg->dsp_vact_st_end,
+ V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch));
- writel(V_HEAP(hsync_len + hback_porch + hactive) |
- V_HASP(hsync_len + hback_porch),
- &preg->post_dsp_hact_info);
+ write32(&preg->post_dsp_hact_info,
+ V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch));
- writel(V_VAEP(vsync_len + vback_porch + vactive)|
- V_VASP(vsync_len + vback_porch),
- &preg->post_dsp_vact_info);
+ write32(&preg->post_dsp_vact_info,
+ V_VAEP(vsync_len + vback_porch + vactive) | V_VASP(vsync_len + vback_porch));
- writel(0x01, &preg->reg_cfg_done); /* enable reg config */
+ write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 21:24:02 +0000