diff options
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra/dc.h | 8 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/dp.c | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/include/soc/clock.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/clock.c | 10 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/dc.c | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/dsi.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/flow_ctrl.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/id.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/mtc.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/power.c | 2 |
12 files changed, 23 insertions, 23 deletions
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index aed8b99cb3..a9061f8ce8 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -512,14 +512,14 @@ struct tegra_dc_mode { u32 vmode; }; -unsigned long READL(void * p); -void WRITEL(unsigned long value, void * p); +unsigned long READL(void *p); +void WRITEL(unsigned long value, void *p); #ifndef __PRE_RAM__ void display_startup(struct device *dev); #endif -void dp_init(void * _config); -void dp_enable(void * _dp); +void dp_init(void *_config); +void dp_enable(void *_dp); unsigned int fb_base_mb(void); #endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index e96a80c384..9173e62000 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -483,7 +483,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, void clock_cpu0_config(void *entry) { - void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + void *const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; write32(&maincpu_stack_pointer, (uintptr_t)_estack); write32(&maincpu_entry_point, (uintptr_t)entry); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index e66cbbd9dc..febb420497 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -38,7 +38,7 @@ struct tegra_dc dc_data; int dump = 0; -unsigned long READL(void * p) +unsigned long READL(void *p) { unsigned long value; @@ -55,7 +55,7 @@ unsigned long READL(void * p) return value; } -void WRITEL(unsigned long value, void * p) +void WRITEL(unsigned long value, void *p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 8a316f2a5c..a9b8d7da97 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -328,7 +328,7 @@ static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, } static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, - u8 * data_ptr) + u8 *data_ptr) { u32 size = 1; u32 status = 0; @@ -1356,7 +1356,7 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp, printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__); } -void dp_init(void * _config) +void dp_init(void *_config) { struct soc_nvidia_tegra124_config *config = (void *)_config; struct tegra_dc *dc = config->dc_data; @@ -1406,7 +1406,7 @@ static int tegra_dp_hpd_plug(struct tegra_dc_dp_data *dp, int timeout_ms) return -1; } -void dp_enable(void * _dp) +void dp_enable(void *_dp) { struct tegra_dc_dp_data *dp = _dp; struct tegra_dc *dc = dp->dc; diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 28d1603fba..d08e26fb80 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -290,7 +290,7 @@ void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq); -void clock_cpu0_config(void * entry); +void clock_cpu0_config(void *entry); void clock_cpu0_remove_reset(void); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 51cfc8b2c8..6ce2ba1291 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -654,7 +654,7 @@ void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, write32(rst_dev_clr_reg, val); } -static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_set), CLK_RST_REG(clk_enb_h_set), CLK_RST_REG(clk_enb_u_set), @@ -664,7 +664,7 @@ static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_y_set), }; -static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_l_clr), CLK_RST_REG(clk_enb_h_clr), CLK_RST_REG(clk_enb_u_clr), @@ -674,7 +674,7 @@ static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(clk_enb_y_clr), }; -static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_set), CLK_RST_REG(rst_dev_h_set), CLK_RST_REG(rst_dev_u_set), @@ -684,7 +684,7 @@ static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_y_set), }; -static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { +static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_l_clr), CLK_RST_REG(rst_dev_h_clr), CLK_RST_REG(rst_dev_u_clr), @@ -694,7 +694,7 @@ static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { CLK_RST_REG(rst_dev_y_clr), }; -static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], +static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS], u32 bits[DEV_CONFIG_BLOCKS]) { int i = 0; diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index b54614f2fe..b892c602b3 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -23,7 +23,7 @@ #include <soc/display.h> int dump = 0; -unsigned long READL(void * p) +unsigned long READL(void *p) { unsigned long value; @@ -40,7 +40,7 @@ unsigned long READL(void * p) return value; } -void WRITEL(unsigned long value, void * p) +void WRITEL(unsigned long value, void *p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 5a9d5a513d..532ffc3122 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -569,7 +569,7 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) return tegra_mipi_calibrate(dsi->mipi); } -static const char * const error_report[16] = { +static const char *const error_report[16] = { "SoT Error", "SoT Sync Error", "EoT Sync Error", diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c index ea5b2795b3..0eb835788a 100644 --- a/src/soc/nvidia/tegra210/flow_ctrl.c +++ b/src/soc/nvidia/tegra210/flow_ctrl.c @@ -36,7 +36,7 @@ #define FLOW_CTRL_CPU1_CSR 0x18 #define FLOW_CTRL_CC4_CORE0_CTRL 0x6c -static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE; +static void *tegra_flowctrl_base = (void *)TEGRA_FLOW_BASE; static const uint8_t flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 0903ba98ef..42b2be6535 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -23,7 +23,7 @@ static inline int context_avp(void) { const uint32_t avp_id = 0xaaaaaaaa; - void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE; + void *const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE; return read32(uptag) == avp_id; } diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index f71e5e8f85..97eb3dee14 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -31,7 +31,7 @@ int tegra210_run_mtc(void) struct region_device fh; struct cbfsf mtc_file; - void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; + void *const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; void *dvfs_table; size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc; diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c index 6b22f5a935..cef5b99b5c 100644 --- a/src/soc/nvidia/tegra210/power.c +++ b/src/soc/nvidia/tegra210/power.c @@ -36,7 +36,7 @@ static int partition_powered(int id) return POWER_GATE; } -static const char * const power_gate_string[] = { +static const char *const power_gate_string[] = { [POWER_GATE] = "Gat", [POWER_UNGATE] = "Ungat", }; |