diff options
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/dp.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/dp.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/mipi_dsi.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/sdram.c | 4 |
8 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 0d1fb19dd2..bc033c9f35 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -54,7 +54,7 @@ struct soc_nvidia_tegra124_config { /* Delay before from power on asserting vdd */ int vdd_delay_ms; - /* Delay beween pwm and backlight_en_gpio is asserted */ + /* Delay between pwm and backlight_en_gpio is asserted */ int pwm_to_bl_delay_ms; /* Delay before HPD high */ diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 4155c34b21..5da2c066f5 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -465,7 +465,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra124_config *config, diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 4fcbaffbee..0244b47def 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -79,7 +79,7 @@ config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE help - Map the UART names to the respective MMIO addres. + Map the UART names to the respective MMIO addresses. config BOOTROM_SDRAM_INIT bool "SoC BootROM does SDRAM init with full BCT" diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index f76ab347e0..5846be9809 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -137,7 +137,7 @@ req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) - $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") endif # BL31 component is placed towards the end of 32-bit address space. This assumes diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 9c55242765..a2b06b160e 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -477,7 +477,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra210_config *config, diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 31ed4f256c..bd9a25c3e6 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -94,7 +94,7 @@ enum { /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); -/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index cd1b822a05..067dc6d618 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -193,7 +193,7 @@ ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, /* * DCS long write packets contain the word count in the header * bytes 1 and 2 and have a payload containing the DCS command - * byte folowed by word count minus one bytes. + * byte followed by word count minus one bytes. * * DCS short write packets encode the DCS command and up to * one parameter in header bytes 1 and 2. diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 8ffa0e500a..702897f1ae 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -155,7 +155,7 @@ static void sdram_set_pad_macros(const struct sdram_params *param, /* * Program CMD mapping. Required before brick mapping, else - * we can't gaurantee CK will be differential at all times. + * we can't guarantee CK will be differential at all times. */ write32(®s->fbio_cfg7, param->EmcFbioCfg7); @@ -979,7 +979,7 @@ static void sdram_set_refresh(const struct sdram_params *param, /* Enable EMC pipe clock gating */ write32(®s->cfg_pipe_clk, param->EmcCfgPipeClk); - /* Depending on freqency, enable CMD/CLK fdpd */ + /* Depending on frequency, enable CMD/CLK fdpd */ write32(®s->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp); } |