diff options
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/addressmap.h | 6 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/pll.h | 7 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/spi.h | 53 |
3 files changed, 66 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d6f54cf5dd..de7eb1f1cb 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -31,6 +31,12 @@ enum { GPT_BASE = IO_PHYS + 0x00008000, APMIXED_BASE = IO_PHYS + 0x0000C000, UART0_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01014000, + SPI5_BASE = IO_PHYS + 0x01015000, IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index d1ceded812..8c0d4e3a2d 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -260,6 +260,13 @@ enum { /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, + MAINPLL_D5_D2_HZ = MAINPLL_D5_HZ / 2, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_D2_HZ, }; #endif /* SOC_MEDIATEK_MT8183_PLL_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h new file mode 100644 index 0000000000..9bc7121847 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_MT8183_SPI_H +#define MTK_MT8183_SPI_H + +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +enum { + SPI_CFG0_CS_HOLD_SHIFT = 0, + SPI_CFG0_CS_SETUP_SHIFT = 16, +}; + +enum { + SPI_CFG2_SCK_LOW_SHIFT = 0, + SPI_CFG2_SCK_HIGH_SHIFT = 16, +}; + + +#endif |