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-rw-r--r--src/soc/intel/cannonlake/Kconfig1
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/cannonlake/pmc.c10
3 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f2a316aba9..8abe930009 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
+ select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index fa75673e45..052847d08c 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -39,6 +39,3 @@
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
-
-/* Intel Power Engine Plug-in */
-#include <soc/intel/common/block/acpi/acpi/pep.asl>
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 59f4be5564..817cdd77dc 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
+#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
@@ -119,10 +120,19 @@ static void soc_acpi_mode_init(struct device *dev)
pmc_set_acpi_mode();
}
+static void pmc_fill_ssdt(const struct device *dev)
+{
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
+ generate_acpi_power_engine();
+}
+
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
.init = soc_acpi_mode_init,
.enable = pmc_init,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt = pmc_fill_ssdt,
+#endif
.scan_bus = scan_static_bus,
};