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-rw-r--r--src/soc/intel/alderlake/chip.h21
-rw-r--r--src/soc/intel/alderlake/chipset.cb24
-rw-r--r--src/soc/intel/alderlake/vr_config.c41
3 files changed, 51 insertions, 35 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 771fc5aaa7..93d8eee7c8 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -21,14 +21,14 @@
/* Types of different SKUs */
enum soc_intel_alderlake_power_limits {
- ADL_P_282_CORE,
- ADL_P_482_CORE,
+ ADL_P_142_242_282_15W_CORE,
+ ADL_P_482_28W_CORE,
ADL_P_682_28W_CORE,
- ADL_P_682_45W_CORE,
+ ADL_P_442_482_45W_CORE,
+ ADL_P_642_682_45W_CORE,
ADL_M_282_12W_CORE,
ADL_M_282_15W_CORE,
ADL_M_242_CORE,
- ADL_P_242_CORE,
ADL_P_442_45W_CORE,
ADL_POWER_LIMITS_COUNT
};
@@ -48,12 +48,15 @@ static const struct {
enum soc_intel_alderlake_power_limits limits;
enum soc_intel_alderlake_cpu_tdps cpu_tdp;
} cpuid_to_adl[] = {
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_28W_CORE, TDP_28W },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_45W_CORE, TDP_45W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 60c149a72d..c956fd4826 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -2,13 +2,13 @@ chip soc/intel/alderlake
device cpu_cluster 0 on end
- register "power_limits_config[ADL_P_282_CORE]" = "{
+ register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 123,
}"
- register "power_limits_config[ADL_P_482_CORE]" = "{
+ register "power_limits_config[ADL_P_482_28W_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 64,
.tdp_pl4 = 90,
@@ -20,7 +20,13 @@ chip soc/intel/alderlake
.tdp_pl4 = 140,
}"
- register "power_limits_config[ADL_P_682_45W_CORE]" = "{
+ register "power_limits_config[ADL_P_442_482_45W_CORE]" = "{
+ .tdp_pl1_override = 45,
+ .tdp_pl2_override = 95,
+ .tdp_pl4 = 125,
+ }"
+
+ register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_pl4 = 215,
@@ -42,18 +48,6 @@ chip soc/intel/alderlake
.tdp_pl4 = 68,
}"
- register "power_limits_config[ADL_P_242_CORE]" = "{
- .tdp_pl1_override = 15,
- .tdp_pl2_override = 55,
- .tdp_pl4 = 123,
- }"
-
- register "power_limits_config[ADL_P_442_45W_CORE]" = "{
- .tdp_pl1_override = 45,
- .tdp_pl2_override = 95,
- .tdp_pl4 = 125,
- }"
-
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index 1964c12193..dbc5f50e20 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -10,8 +10,7 @@
/*
* VR Configurations for IA and GT domains for ADL-P SKU's.
- * Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation
- * for ADL-P 482(28W) and 442(45W).
+ * Per doc#627345 ADL_P Partial Intel PlatformDesignStudio Rev 2.0.0, update PD
*
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
@@ -19,11 +18,19 @@
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
- * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 |
+ * | | GT | 3.2 | 3.2 | 55 | 57 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
- * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 40 | 28000 |
+ * | ADL-P 482(45W) | IA | 2.3 | 2.3 | 120 | 47 | 28000 |
+ * + 442(45W) +-----------+-------+-------+---------+-------------+----------+
+ * | | GT | 3.2 | 3.2 | 55 | 47 | 28000 |
+ * +----------------+-----------+-------+-------+---------+-------------+----------+
+ * | ADL-P 682(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 |
+ * + +-----------+-------+-------+---------+-------------+----------+
+ * | | GT | 3.2 | 3.2 | 55 | 40 | 28000 |
+ * +----------------+-----------+-------+-------+---------+-------------+----------+
+ * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 32 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
- * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 |
+ * | | GT | 3.2 | 3.2 | 55 | 32 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
@@ -54,37 +61,49 @@ static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, c
static const struct vr_lookup vr_config_ll[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
};
static const struct vr_lookup vr_config_icc[] = {
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 50) },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 50) },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(111, 50) },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 50) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
};
static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
};
static const struct vr_lookup vr_config_tdc_currentlimit[] = {
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
- { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
+ { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
};
void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 10:40:38 +0000