3 files changed, 1 insertions, 35 deletions
diff --git a/src/soc/intel/cannonlake/acpi/cnvi.asl b/src/soc/intel/cannonlake/acpi/cnvi.asl
deleted file mode 100644
index f9aeeb06e0..0000000000
--- a/src/soc/intel/cannonlake/acpi/cnvi.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/pm.h>
-
-/* CNVi Controller 0:14.3 */
-Device (CNVI) {
-	 Name(_ADR, 0x00140003)
-
-	Name (_S3D, 3)  /* D3 supported in S3 */
-	Name (_S0W, 3)  /* D3 can wake device in S0 */
-	Name (_S3W, 3)  /* D3 can wake system from S3 */
-
-	Name (_PRW, Package() { PME_B0_EN_BIT, 3 })
-
-	Method (_STA, 0)
-	{
-		Return (0xF)
-	}
-}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 49b5f6e509..eabff66738 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -60,8 +60,5 @@
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
 
-/* CNVi */
-#include "cnvi.asl"
-
 /* GBe 0:1f.6 */
 #include "pch_glan.asl"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 74cb833bf6..2deb35fdb8 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -25,6 +25,7 @@
 #include <soc/gpio.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>