6 files changed, 97 insertions, 12 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 7950b814fb..9589e5a88b 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -5,7 +5,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
 subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
 subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
 
-bootblock-y += bootblock.c spi.c lpc.c gpio.c
+bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
 romstage-y += romstage.c reset.c util.c spi.c gpio.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
 postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 7f14be6329..72d9742af8 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -9,6 +9,7 @@
 #include <cpu/x86/mtrr.h>
 #include <intelblocks/lpc_lib.h>
 #include <soc/pci_devs.h>
+#include <soc/bootblock.h>
 
 const FSPT_UPD temp_ram_init_params = {
 	.FspUpdHeader = {
@@ -53,4 +54,5 @@ void bootblock_soc_init(void)
 {
 	if (CONFIG(BOOTBLOCK_CONSOLE))
 		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
+	bootblock_pch_init();
 }
diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h
new file mode 100644
index 0000000000..6be4370454
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_XEON_SP_BOOTBLOCK_H_
+#define _SOC_XEON_SP_BOOTBLOCK_H_
+
+#include "iomap.h"
+
+/* Bootblock post console init programming */
+void bootblock_pch_init(void);
+
+#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h
new file mode 100644
index 0000000000..84d5e4896b
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/pch.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PCH_H_
+#define _SOC_PCH_H_
+
+#include <device/device.h>
+
+#if ENV_RAMSTAGE
+void pch_disable_devfn(struct device *dev);
+#endif
+
+#endif /* _SOC_PCH_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h
index 74343f84c8..d3bad1b715 100644
--- a/src/soc/intel/xeon_sp/include/soc/pmc.h
+++ b/src/soc/intel/xeon_sp/include/soc/pmc.h
@@ -3,18 +3,28 @@
 #ifndef _SOC_PMC_H_
 #define _SOC_PMC_H_
 
-/* PCI Configuration Space (D31:F2): PMC */
-#define PMC_ACPI_CNT            0x44
+ /* PCI Configuration Space (D31:F2): PMC */
+#define ABASE			0x40
+#define ACTL			0x44
+#define PMC_ACPI_CNT 0x44
+#define  PWRM_EN		(1 << 8)
+#define  ACPI_EN		(1 << 7)
+#define  SCI_IRQ_SEL		(7 << 0)
+#define SCI_IRQ_ADJUST		0
 
-#define  SCI_IRQ_SEL            (7 << 0)
-#define  SCIS_IRQ9              0
-#define  SCIS_IRQ10             1
-#define  SCIS_IRQ11             2
-#define  SCIS_IRQ20             4
-#define  SCIS_IRQ21             5
-#define  SCIS_IRQ22             6
-#define  SCIS_IRQ23             7
+#define  SCIS_IRQ9		0
+#define  SCIS_IRQ10		1
+#define  SCIS_IRQ11		2
+#define  SCIS_IRQ20		4
+#define  SCIS_IRQ21		5
+#define  SCIS_IRQ22		6
+#define  SCIS_IRQ23		7
+#define PWRMBASE		0x48
+#define GEN_PMCON_A		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_B		0xa4
+#define  SLP_STR_POL_LOCK	(1 << 18)
+#define  ACPI_BASE_LOCK		(1 << 17)
 
-#define SCI_IRQ_ADJUST          0
 
 #endif
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c
new file mode 100644
index 0000000000..5427952688
--- /dev/null
+++ b/src/soc/intel/xeon_sp/pch.c
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
+#include <soc/bootblock.h>
+#include <soc/pmc.h>
+#include <console/console.h>
+
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
+#define PCR_DMI_ACPIBA		0x27B4
+#define PCR_DMI_ACPIBDID	0x27B8
+#define PCR_DMI_PMBASEA		0x27AC
+#define PCR_DMI_PMBASEC		0x27B0
+
+static void soc_config_acpibase(void)
+{
+	uint32_t reg32;
+
+	/* Disable ABASE in PMC Device first before changing Base Address */
+	reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
+	pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
+
+	/* Program ACPI Base */
+	pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
+
+	/* Enable ACPI in PMC */
+	pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
+
+	uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
+	printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
+	/*
+	 * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
+	 * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
+	 */
+	reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
+	pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
+	pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
+}
+
+void bootblock_pch_init(void)
+{
+	/*
+	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
+	 */
+	soc_config_acpibase();
+}