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-rw-r--r--src/soc/intel/baytrail/include/soc/romstage.h1
-rw-r--r--src/soc/intel/baytrail/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/baytrail/romstage/early_spi.c60
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h1
-rw-r--r--src/soc/intel/braswell/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/braswell/romstage/early_spi.c63
-rw-r--r--src/soc/intel/broadwell/include/soc/romstage.h3
-rw-r--r--src/soc/intel/broadwell/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/broadwell/romstage/spi.c143
9 files changed, 0 insertions, 274 deletions
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 3e8b6a27ef..fffce7e317 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -37,7 +37,6 @@ void gfx_init(void);
void tco_disable(void);
void punit_init(void);
void set_max_freq(void);
-int early_spi_read_wpsr(u8 *sr);
#if CONFIG(ENABLE_BUILTIN_COM1)
void byt_config_com1_and_enable(void);
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index f1a3463d20..d43a6fb6e3 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -5,4 +5,3 @@ romstage-y += raminit.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
romstage-y += gfx.c
romstage-y += pmc.c
-romstage-y += early_spi.c
diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c
deleted file mode 100644
index 72e9b2cdae..0000000000
--- a/src/soc/intel/baytrail/romstage/early_spi.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <console/console.h>
-
-#include <soc/iomap.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
-
-#define SPI_CYCLE_DELAY 10 /* 10us */
-#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */
-
-#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x))
-#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x))
-#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x))
-
-/* Minimal set of commands to read wpsr from SPI. Don't use this code outside
- * romstage -- it trashes the opmenu table.
- * Returns 0 on success, < 0 on failure. */
-int early_spi_read_wpsr(u8 *sr)
-{
- int timeout = SPI_CYCLE_TIMEOUT;
-
- /* No address associated with rdsr */
- SPI8(OPTYPE) = 0x0;
- /* Setup opcode[0] = read wpsr */
- SPI8(OPMENU0) = 0x5;
-
- /* Start transaction */
- SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
-
- /* Wait for error / complete status */
- while (timeout--) {
- u16 status = SPI16(SSFS);
- if (status & FLASH_CYCLE_ERROR) {
- printk(BIOS_ERR, "SPI rdsr failed\n");
- return -1;
- } else if (status & CYCLE_DONE_STATUS)
- break;
-
- udelay(SPI_CYCLE_DELAY);
- }
-
- *sr = SPI32(FDATA0) & 0xff;
- return 0;
-}
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 633233e6c6..4ecbd2c1f9 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -25,7 +25,6 @@
void gfx_init(void);
void tco_disable(void);
void punit_init(void);
-int early_spi_read_wpsr(u8 *sr);
void set_max_freq(void);
/* romstage_common.c functions */
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc
index c3ed415dcc..15de822041 100644
--- a/src/soc/intel/braswell/romstage/Makefile.inc
+++ b/src/soc/intel/braswell/romstage/Makefile.inc
@@ -1,3 +1,2 @@
-romstage-y += early_spi.c
romstage-y += pmc.c
romstage-y += romstage.c
diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c
deleted file mode 100644
index 0ca5ef521f..0000000000
--- a/src/soc/intel/braswell/romstage/early_spi.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc. All rights reserved.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <console/console.h>
-
-#include <soc/iomap.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
-
-#define SPI_CYCLE_DELAY 10 /* 10us */
-#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */
-
-#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x))))
-#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x))))
-#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x))))
-
-/*
- * Minimal set of commands to read wpsr from SPI. Don't use this code outside
- * romstage -- it trashes the opmenu table.
- * Returns 0 on success, < 0 on failure.
- */
-int early_spi_read_wpsr(u8 *sr)
-{
- int timeout = SPI_CYCLE_TIMEOUT;
-
- /* No address associated with rdsr */
- SPI8(OPTYPE) = 0x0;
- /* Setup opcode[0] = read wpsr */
- SPI8(OPMENU0) = 0x5;
-
- /* Start transaction */
- SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO;
-
- /* Wait for error / complete status */
- while (timeout--) {
- u16 status = SPI16(SSFS);
- if (status & FLASH_CYCLE_ERROR) {
- printk(BIOS_ERR, "SPI rdsr failed\n");
- return -1;
- } else if (status & CYCLE_DONE_STATUS)
- break;
-
- udelay(SPI_CYCLE_DELAY);
- }
-
- *sr = SPI32(FDATA0) & 0xff;
- return 0;
-}
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index ac8265fb4c..cd37cf6316 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -46,7 +46,4 @@ void intel_early_me_status(void);
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-int early_spi_read(u32 offset, u32 size, u8 *buffer);
-int early_spi_read_wpsr(u8 *sr);
-
#endif
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc
index ea17d67061..a53cd95cd5 100644
--- a/src/soc/intel/broadwell/romstage/Makefile.inc
+++ b/src/soc/intel/broadwell/romstage/Makefile.inc
@@ -6,6 +6,5 @@ romstage-y += raminit.c
romstage-y += report_platform.c
romstage-y += romstage.c
romstage-y += smbus.c
-romstage-y += spi.c
romstage-y += systemagent.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c
deleted file mode 100644
index cb0509d104..0000000000
--- a/src/soc/intel/broadwell/romstage/spi.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <delay.h>
-#include <soc/spi.h>
-#include <soc/rcba.h>
-#include <soc/romstage.h>
-
-#define SPI_DELAY 10 /* 10us */
-#define SPI_RETRY 200000 /* 2s */
-
-static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
-{
- u32 *ptr32 = (u32 *)buffer;
- u32 i;
-
- /* Clear status bits */
- SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
- SPIBAR_HSFS_FDONE;
-
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
- printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
- return -1;
- }
-
- /* Set flash address */
- SPIBAR32(SPIBAR_FADDR) = offset;
-
- /* Setup read transaction */
- SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
- SPIBAR_HSFC_CYCLE_READ;
-
- /* Start transaction */
- SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
-
- /* Wait for completion */
- for (i = 0; i < SPI_RETRY; i++) {
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
- /* Cycle in progress, wait 1ms */
- udelay(SPI_DELAY);
- continue;
- }
-
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
- printk(BIOS_ERR, "SPI ERROR: Access Error\n");
- return -1;
-
- }
-
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
- printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
- return -1;
- }
- break;
- }
-
- if (i >= SPI_RETRY) {
- printk(BIOS_ERR, "SPI ERROR: Timeout\n");
- return -1;
- }
-
- /* Read the data */
- for (i = 0; i < size; i += sizeof(u32)) {
- if (size-i >= 4) {
- /* reading >= dword */
- *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
- } else {
- /* reading < dword */
- u8 j, *ptr8 = (u8 *)ptr32;
- u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
- for (j = 0; j < (size-i); j++) {
- *ptr8++ = temp & 0xff;
- temp >>= 8;
- }
- }
- }
-
- return size;
-}
-
-int early_spi_read(u32 offset, u32 size, u8 *buffer)
-{
- u32 current = 0;
-
- while (size > 0) {
- u8 count = (size < 64) ? size : 64;
- if (early_spi_read_block(offset + current, count,
- buffer + current) < 0)
- return -1;
- size -= count;
- current += count;
- }
-
- return 0;
-}
-
-/*
- * Minimal set of commands to read WPSR from SPI.
- * Don't use this code outside romstage -- it trashes the opmenu table.
- * Returns 0 on success, < 0 on failure.
- */
-int early_spi_read_wpsr(u8 *sr)
-{
- int retry;
-
- /* No address associated with rdsr */
- SPIBAR8(SPIBAR_OPTYPE) = 0x0;
- /* Setup opcode[0] = read wpsr */
- SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5;
-
- /* Start transaction */
- SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO;
-
- /* Wait for error / complete status */
- for (retry = SPI_RETRY; retry; retry--) {
- u16 status = SPIBAR16(SPIBAR_SSFS);
- if (status & SPIBAR_SSFS_ERROR) {
- printk(BIOS_ERR, "SPI rdsr failed\n");
- return -1;
- } else if (status & SPIBAR_SSFS_DONE) {
- break;
- }
-
- udelay(SPI_DELAY);
- }
-
- *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff;
- return 0;
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 19:21:35 +0000