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-rw-r--r--src/soc/intel/quark/Kconfig118
1 files changed, 118 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 1bfab49c95..802f972058 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -29,6 +29,42 @@ config CPU_SPECIFIC_OPTIONS
select USE_MARCH_586
#####
+# Debug support
+# The following options provide debug support for the Quark coreboot
+# code. The SD LED is used as a binary marker to determine if a
+# specific point in the execution flow has been reached.
+#####
+
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output
+ is available. Setting this LED indicates that control has reached the
+ desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
+#####
# Flash layout
# Specify the size of the coreboot file system in the read-only
# (recovery) portion of the flash part.
@@ -45,6 +81,88 @@ config CBFS_SIZE
- Intel Trusted Execution Engine firmware
#####
+# FSP binary
+# The following options control the FSP binary file placement in
+# the flash image and ESRAM. This file is required by the Quark
+# SoC code to boot coreboot and its payload.
+#####
+
+config ADD_FSP_RAW_BIN
+ bool "Add the Intel FSP binary to the flash image without relocation"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
+config FSP_FILE
+ string "Intel FSP binary path and filename"
+ default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_RAW_BIN
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+ string "8 byte platform string identifying the FSP platform"
+ default "QUK-FSP0"
+ depends on PLATFORM_USES_FSP1_1
+ help
+ 8 ASCII character byte signature string that will help match the FSP
+ binary to a supported hardware configuration.
+
+config FSP_LOC
+ hex
+ default 0xfff80000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with Intel's BCT (tool).
+
+config FSP_ESRAM_LOC
+ hex
+ default 0x80000000
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The location in ESRAM where a copy of the FSP binary is placed.
+
+#####
+# FSP PDAT binary
+# The following options control the FSP platform data binary
+# file placement in the flash image.
+#####
+
+config ADD_FSP_PDAT_FILE
+ bool "Should the PDAT binary be added to the flash image?"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ The PDAT file is required for the FSP 1.1 binary
+
+config FSP_PDAT_FILE
+ string
+ default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The path and filename of the Intel Galileo platform-data-patch (PDAT)
+ binary. This binary file is generated by the platform-data-patch.py
+ script released with the Quark BSP and contains the Ethernet address.
+
+config FSP_PDAT_LOC
+ hex
+ default 0xfff10000
+ depends on PLATFORM_USES_FSP1_1
+ depends on ADD_FSP_PDAT_FILE
+ help
+ The location in CBFS that the PDAT is located. It must match the
+ PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+#####
# RMU binary
# The following options control the Quark chipset microcode file
# placement in the flash image. This file is required to bring