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Diffstat (limited to 'src/soc/intel/jasperlake')
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c16
1 files changed, 5 insertions, 11 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index d68494f290..bb41b28f15 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -70,17 +70,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
/* Chipset Lockdown */
- if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
- params->PchLockDownGlobalSmi = 0;
- params->PchLockDownBiosInterface = 0;
- params->PchUnlockGpioPads = 1;
- params->RtcMemoryLock = 0;
- } else {
- params->PchLockDownGlobalSmi = 1;
- params->PchLockDownBiosInterface = 1;
- params->PchUnlockGpioPads = 0;
- params->RtcMemoryLock = 1;
- }
+ const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
+ params->PchLockDownGlobalSmi = lockdown_by_fsp;
+ params->PchLockDownBiosInterface = lockdown_by_fsp;
+ params->PchUnlockGpioPads = !lockdown_by_fsp;
+ params->RtcMemoryLock = lockdown_by_fsp;
/* coreboot will send EOP before loading payload */
params->EndOfPostMessage = EOP_DISABLE;