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-rw-r--r--src/soc/intel/common/block/cse/cse.c4
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h8
2 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index d284a9d638..e01b1cf920 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -85,11 +85,11 @@ static uintptr_t get_cse_bar(pci_devfn_t dev)
}
/*
- * Initialize the device with provided temporary BAR. If BAR is 0 use a
+ * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a
* default. This is intended for pre-mem usage only where BARs haven't been
* assigned yet and devices are not enabled.
*/
-void heci_init(uintptr_t tempbar)
+void cse_init(uintptr_t tempbar)
{
pci_devfn_t dev = PCH_DEV_CSE;
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 8fd8ba0e1a..28bc2503be 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -326,8 +326,12 @@ struct cse_boot_perf_rsp {
uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA];
} __packed;
-/* set up device for use in early boot enviroument with temp bar */
-void heci_init(uintptr_t bar);
+/*
+ * Initialize the CSE device.
+ *
+ * Set up CSE device for use in early boot environment with temp bar.
+ */
+void cse_init(uintptr_t bar);
/*
* Send message from BIOS_HOST_ADDR to cse_addr.