diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index d605625bc5..44c873c8e5 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -269,11 +269,6 @@ Device (PDRC) */ Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB) - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - /* VTD engine memory range. */ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) @@ -301,12 +296,6 @@ Device (PDRC) CreateDwordField (BUF0, EGPB._BAS, EBR0) EBR0 = \_SB.PCI0.GEPB () - CreateDwordField (BUF0, PCIX._BAS, XBR0) - XBR0 = \_SB.PCI0.GPCB () - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - XSZ0 = \_SB.PCI0.GPCL () - CreateDwordField (BUF0, FIOH._BAS, FBR0) FBR0 = 0x100000000 - CONFIG_ROM_SIZE |