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-rw-r--r--src/soc/intel/cannonlake/cpu.c8
-rw-r--r--src/soc/intel/cannonlake/include/soc/msr.h2
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 4f6720850e..6af3e1a56f 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -20,6 +20,14 @@
#include "chip.h"
+bool cpu_soc_is_in_untrusted_mode(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_BIOS_DONE);
+ return !!(msr.lo & ENABLE_IA_UNTRUSTED);
+}
+
static void soc_fsp_load(void)
{
fsps_load();
diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index 1c902d5abb..cc95fe6845 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -5,6 +5,8 @@
#include <intelblocks/msr.h>
+#define MSR_BIOS_DONE 0x151
+#define ENABLE_IA_UNTRUSTED (1 << 0)
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_PL3_CONTROL 0x615
#define MSR_VR_MISC_CONFIG2 0x636