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Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
-rw-r--r-- | src/soc/intel/braswell/Kconfig | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba2ac68bf8..5b6a9237e7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -104,17 +104,6 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - help - The haswell romstage code caches the loaded ramstage program - in SMM space. On S3 wake the romstage will copy over a fresh - ramstage that was cached in the SMM space. This option determines - the action to take when the ramstage cache is invalid. If selected - the system will reset otherwise the ramstage will be reloaded from - cbfs. - config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n |