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-rw-r--r--src/soc/intel/alderlake/fsp_params.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index e3222be02e..f14adbdc83 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -673,6 +673,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
if (rp_cfg->pcie_rp_aspm)
s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
+ /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
+ if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
+ s_cfg->PcieRpSlotImplemented[i] = 0;
+ s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
}
}