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-rw-r--r--src/soc/intel/alderlake/acpi/tcss.asl1
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_pcierp.asl20
2 files changed, 1 insertions, 20 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 87aeb73b8d..0890e4048c 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <soc/iomap.h>
+#include <soc/tcss.h>
/*
* Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index dee265c3a3..7336e162a8 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -1,25 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
- * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
- * port of the USB4/TBT topology.
- */
-/* Number of microseconds to wait after a conventional reset */
-#define FW_RESET_TIME 50000
-
-/* Number of microseconds to wait after data link layer active report */
-#define FW_DL_UP_TIME 1
-
-/* Number of microseconds to wait after a function level reset */
-#define FW_FLR_RESET_TIME 1
-
-/* Number of microseconds to wait from D3 hot to D0 transition */
-#define FW_D3HOT_TO_D0_TIME 50000
-
-/* Number of microseconds to wait after setting the VF enable bit */
-#define FW_VF_ENABLE_TIME 1
-
OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
Field (PXCS, AnyAcc, NoLock, Preserve)
{