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-rw-r--r--src/soc/amd/common/block/psp/psp_gen2.c4
-rw-r--r--src/soc/amd/stoneyridge/cpu.c4
-rw-r--r--src/soc/amd/stoneyridge/psp.c4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 95adce40d2..e2f51d8206 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -13,9 +13,9 @@
static uintptr_t soc_get_psp_base_address(void)
{
- uintptr_t psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
+ uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio)
- printk(BIOS_ERR, "PSP: MSR_PSP_ADDR uninitialized\n");
+ printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n");
return psp_mmio;
}
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 17fd9b97bb..d943deb69a 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -76,10 +76,10 @@ static void model_15_init(struct device *dev)
uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
- psp_msr = rdmsr(MSR_PSP_ADDR);
+ psp_msr = rdmsr(PSP_ADDR_MSR);
if (psp_msr.lo == 0) {
psp_msr.lo = psp_bar;
- wrmsr(MSR_PSP_ADDR, psp_msr);
+ wrmsr(PSP_ADDR_MSR, psp_msr);
}
}
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index cd14d7bf69..8d6290f619 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -45,9 +45,9 @@ void *soc_get_mbox_address(void)
/* Determine if Bar3Hide has been set, and if hidden get the base from
* the MSR instead. */
if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
- psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
+ psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio) {
- printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
+ printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n");
return 0;
}
} else {