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-rw-r--r--src/soc/amd/stoneyridge/acpi/mmio.asl (renamed from src/soc/amd/stoneyridge/acpi/sb_fch.asl)0
-rw-r--r--src/soc/amd/stoneyridge/acpi/soc.asl4
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl
index ef2b4eab62..ef2b4eab62 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/mmio.asl
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
index 47d5992272..6e67f5a3fa 100644
--- a/src/soc/amd/stoneyridge/acpi/soc.asl
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -15,8 +15,8 @@ Scope(PCI0) {
/* Describe PCI INT[A-H] for the Southbridge */
#include "pci_int.asl"
-/* Describe the devices in the Southbridge */
-#include "sb_fch.asl"
+/* Describe the MMIO devices in the FCH */
+#include "mmio.asl"
/* Add GPIO library */
#include <soc/amd/common/acpi/gpio_bank_lib.asl>