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-rw-r--r--src/soc/amd/sabrina/acpi.c6
-rw-r--r--src/soc/amd/sabrina/include/soc/msr.h4
2 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/amd/sabrina/acpi.c b/src/soc/amd/sabrina/acpi.c
index b10773b7d5..32bbde5364 100644
--- a/src/soc/amd/sabrina/acpi.c
+++ b/src/soc/amd/sabrina/acpi.c
@@ -187,12 +187,12 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
(pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT;
/* Voltage */
- if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) {
- /* Voltage off for VID codes 0xF8 to 0xFF */
+ if (core_vid == 0x00) {
+ /* Voltage off for VID code 0x00 */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
- SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+ SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */
diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h
index bdc7a14c40..9dba2697e2 100644
--- a/src/soc/amd/sabrina/include/soc/msr.h
+++ b/src/soc/amd/sabrina/include/soc/msr.h
@@ -21,6 +21,10 @@
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
+/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
+#define SERIAL_VID_DECODE_MICROVOLTS 5000
+#define SERIAL_VID_BASE_MICROVOLTS 245000L
+
#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7
#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8