diff options
Diffstat (limited to 'src/soc/amd/common/block/i2c')
| -rw-r--r-- | src/soc/amd/common/block/i2c/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i2c_pad_ctrl.c | 45 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i2c_pad_def.h | 38 |
4 files changed, 90 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 5d8498c6af..7c1ea0edd8 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -2,3 +2,9 @@ config SOC_AMD_COMMON_BLOCK_I2C bool help Select this option to add FCH I2C controller functions to the build. + +config SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + bool + help + Select this option to add FCH I2C pad configuration functions to the + build. diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc index 8af77965ce..3d2cdf6e09 100644 --- a/src/soc/amd/common/block/i2c/Makefile.inc +++ b/src/soc/amd/common/block/i2c/Makefile.inc @@ -1 +1,2 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c diff --git a/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c new file mode 100644 index 0000000000..cdb7900ee6 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <types.h> +#include "i2c_pad_def.h" + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl) +{ + uint32_t pad_ctrl; + + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); + + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; + + switch (ctrl->rx_level) { + case I2C_PAD_RX_NO_CHANGE: + break; + case I2C_PAD_RX_OFF: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_OFF; + break; + case I2C_PAD_RX_3_3V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; + break; + case I2C_PAD_RX_1_8V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_1_8V; + break; + default: + printk(BIOS_WARNING, "Invalid I2C pad RX level for bus %u\n", bus); + break; + } + + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? + I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); +} diff --git a/src/soc/amd/common/block/i2c/i2c_pad_def.h b/src/soc/amd/common/block/i2c/i2c_pad_def.h new file mode 100644 index 0000000000..76e10cd545 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_def.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_I2C_PAD_DEF_H +#define AMD_BLOCK_I2C_PAD_DEF_H + +#include <types.h> + +#define MISC_I2C0_PAD_CTRL 0xd8 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) + +#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define I2C_PAD_CTRL_NG_NORMAL 0xc +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) +#define I2C_PAD_CTRL_RX_SHIFT 4 +#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 +#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) +#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) +#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ +#define I2C_PAD_CTRL_CAP_DOWN BIT(12) +#define I2C_PAD_CTRL_CAP_UP BIT(13) +#define I2C_PAD_CTRL_RES_DOWN BIT(14) +#define I2C_PAD_CTRL_RES_UP BIT(15) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_SPARE0 BIT(17) +#define I2C_PAD_CTRL_SPARE1 BIT(18) +/* The following bits are reserved in Picasso and Cezanne */ +#define I2C_PAD_CTRL_PD_EN BIT(19) +#define I2C_PAD_CTRL_COMP_SEL BIT(20) +#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21) + +#endif /* AMD_BLOCK_I2C_PAD_DEF_H */ |