6 files changed, 51 insertions, 10 deletions
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index 5877b0e922..7b3917da97 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized)
 
 	Return (MCRS)
 }
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/i945_pci_irqs.asl"
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index b8a225562b..d3539b86e6 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -117,6 +117,22 @@ static void pci_domain_set_resources(struct device *dev)
 	assign_resources(dev->link_list);
 }
 
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+
+	if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+		return NULL;
+
+	switch (dev->path.pci.devfn) {
+	case PCI_DEVFN(0, 0):
+		return "MCHC";
+	}
+
+	return NULL;
+}
+
 	/* TODO We could determine how many PCIe busses we need in
 	 * the bar. For now that number is hardcoded to a max of 64.
 	 * See e7525/northbridge.c for an example.
@@ -127,6 +143,7 @@ static struct device_operations pci_domain_ops = {
 	.enable_resources = NULL,
 	.init             = NULL,
 	.scan_bus         = pci_domain_scan_bus,
+	.acpi_name        = northbridge_acpi_name,
 };
 
 static void mc_read_resources(struct device *dev)
@@ -154,7 +171,6 @@ static void intel_set_subsystem(struct device *dev, unsigned int vendor,
 				((device & 0xffff) << 16) | (vendor & 0xffff));
 	}
 }
-
 static struct pci_operations intel_pci_ops = {
 	.set_subsystem    = intel_set_subsystem,
 };
diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl
index d759514bbf..3eff101d99 100644
--- a/src/northbridge/intel/pineview/acpi/hostbridge.asl
+++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl
@@ -230,6 +230,3 @@ Method (_CRS, 0, Serialized)
 
 	Return (MCRS)
 }
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/pineview_pci_irqs.asl"
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 93c7558931..0bba03da29 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -147,12 +147,29 @@ static void mch_domain_init(struct device *dev)
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 }
 
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+
+	if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+		return NULL;
+
+	switch (dev->path.pci.devfn) {
+	case PCI_DEVFN(0, 0):
+		return "MCHC";
+	}
+
+	return NULL;
+}
+
 static struct device_operations pci_domain_ops = {
 	.read_resources   = mch_domain_read_resources,
 	.set_resources    = mch_domain_set_resources,
 	.init             = mch_domain_init,
 	.scan_bus         = pci_domain_scan_bus,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
+	.acpi_name        = northbridge_acpi_name,
 };
 
 static void cpu_bus_init(struct device *dev)
diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl
index 530fdfafd9..90f15c78c1 100644
--- a/src/northbridge/intel/x4x/acpi/hostbridge.asl
+++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl
@@ -229,6 +229,3 @@ Method (_CRS, 0, Serialized)
 
 	Return (MCRS)
 }
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/x4x_pci_irqs.asl"
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 3e5022962a..0fcc297639 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -156,6 +156,22 @@ static void mch_domain_init(struct device *dev)
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 }
 
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
+		return "PCI0";
+
+	if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+		return NULL;
+
+	switch (dev->path.pci.devfn) {
+	case PCI_DEVFN(0, 0):
+		return "MCHC";
+	}
+
+	return NULL;
+}
+
 static struct device_operations pci_domain_ops = {
 	.read_resources   = mch_domain_read_resources,
 	.set_resources    = mch_domain_set_resources,
@@ -163,6 +179,7 @@ static struct device_operations pci_domain_ops = {
 	.scan_bus         = pci_domain_scan_bus,
 	.write_acpi_tables = northbridge_write_acpi_tables,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
+	.acpi_name        = northbridge_acpi_name,
 };