diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 9ef491baed..4e958150dd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -693,9 +693,9 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { - mch_cas = (u16) ((ctrl->CAS - 4) << 1); + mch_cas = (u16)((ctrl->CAS - 4) << 1); } else { - mch_cas = (u16) (ctrl->CAS - 12); + mch_cas = (u16)(ctrl->CAS - 12); mch_cas = ((mch_cas << 1) | 0x1); } @@ -1732,7 +1732,7 @@ static void train_write_flyby(ramctr_timing *ctrl) FOR_ALL_LANES { u64 res = mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); - res |= ((u64) mchbar_read32(lane_base[lane] + + res |= ((u64)mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 7141116840..a46390ca28 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -555,7 +555,7 @@ static void dram_freq(ramctr_timing *ctrl) * Exit early to prevent a system hang. */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2) return; @@ -577,7 +577,7 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 3 - Verify lock frequency */ reg1 = mchbar_read32(MC_BIOS_DATA); - val2 = (u8) reg1; + val2 = (u8)reg1; if (val2 >= ctrl->FRQ) { printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); |