diff options
Diffstat (limited to 'src/northbridge/amd/gx2')
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 9 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 17 |
2 files changed, 7 insertions, 19 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index b84e62e8b2..0e3a3caf95 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -122,9 +122,14 @@ static void pll_reset(void) /* get CPU core clock in MHZ */ cpu_core = calibrate_tsc(); - get_memory_speed(); + print_debug("Cpu core is "); + print_debug_hex32(cpu_core); + print_debug("\n"); + //get_memory_speed(); //msr = rdmsr(GLCP_SYS_RSTPLL); msr = rdmsr(0x4c000014); + print_debug("4c000014 is "); + print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); print_debug("\n"); if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) { print_debug("disable PLL bypass\n\r"); @@ -162,7 +167,7 @@ static void pll_reset(void) print_debug("\n\r"); //gliu = get_memory_speed(); - get_memory_speed(); + //get_memory_speed(); //print_debug("Target Memory Clock "); //print_debug_hex32(gliu); //print_debug("\n\r"); diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 95ce72a10e..a2cc474a3a 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -4,10 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - -} /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */ @@ -16,19 +12,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) int i; msr_t msr; - /* 1. Initialize GLMC registers base on SPD values, - * Hard coded as XpressROM for now */ - //print_debug("sdram_enable step 1\r\n"); - msr = rdmsr(0x20000018); - msr.hi = 0x10076013; - msr.lo = 0x00003000; - wrmsr(0x20000018, msr); - - msr = rdmsr(0x20000019); - msr.hi = 0x18000108; - msr.lo = 0x696332a3; - wrmsr(0x20000019, msr); - /* 2. clock gating for PMode */ msr = rdmsr(0x20002004); msr.lo &= ~0x04; |