diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 13 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 10 |
2 files changed, 11 insertions, 12 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 5df3947e9d..4fdc7b4839 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -141,12 +141,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" - # Enable SATA - register "SataSalpSupport" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsEnableDitoConfig[1]" = "1" - register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -462,7 +456,12 @@ chip soc/intel/tigerlake device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + end device ref pcie_rp7 on end device ref pcie_rp8 on probe DB_SD SD_GL9755S diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index f03f67734c..7c60f0c9c3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -59,10 +59,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # enabling EDP in PortA register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -267,7 +263,11 @@ chip soc/intel/tigerlake device ref csme2 off end device ref heci3 off end device ref heci4 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + end device ref i2c4 off end device ref i2c5 on end device ref uart2 on end |