diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/system76/rpl/Kconfig | 11 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/Kconfig.name | 3 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/dsdt.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/board.fmd | 12 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/board_info.txt | 2 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/data.vbt | bin | 0 -> 9216 bytes | |||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/gpio.c | 227 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/gpio_early.c | 16 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/hda_verb.c | 263 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/overridetree.cb | 97 | ||||
| -rw-r--r-- | src/mainboard/system76/rpl/variants/oryp11/romstage.c | 29 |
11 files changed, 663 insertions, 0 deletions
diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index b2058d4bf2..f3f56e71ed 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -26,6 +26,13 @@ config BOARD_SYSTEM76_GAZE18 select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P +config BOARD_SYSTEM76_ORYP11 + select BOARD_SYSTEM76_RPL_COMMON + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + if BOARD_SYSTEM76_RPL_COMMON config MAINBOARD_DIR @@ -33,18 +40,22 @@ config MAINBOARD_DIR config VARIANT_DIR default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Gazelle" if BOARD_SYSTEM76_GAZE18 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 config MAINBOARD_VERSION default "gaze18" if BOARD_SYSTEM76_GAZE18 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config CONSOLE_POST default y diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index 5bccbd2b47..aa267e7b10 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_SYSTEM76_GAZE18 bool "gaze18" + +config BOARD_SYSTEM76_ORYP11 + bool "oryp11" diff --git a/src/mainboard/system76/rpl/dsdt.asl b/src/mainboard/system76/rpl/dsdt.asl index df4681b4e6..addb4df14d 100644 --- a/src/mainboard/system76/rpl/dsdt.asl +++ b/src/mainboard/system76/rpl/dsdt.asl @@ -19,6 +19,9 @@ DefinitionBlock( { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> + #if CONFIG(BOARD_SYSTEM76_ORYP11) + #include <soc/intel/alderlake/acpi/tcss.asl> + #endif // CONFIG(BOARD_SYSTEM76_ORYP11) } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/rpl/variants/oryp11/board.fmd b/src/mainboard/system76/rpl/variants/oryp11/board.fmd new file mode 100644 index 0000000000..fdf1ebdf52 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 4824K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/board_info.txt b/src/mainboard/system76/rpl/variants/oryp11/board_info.txt new file mode 100644 index 0000000000..37f71e1fa6 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp11 +Release year: 2023 diff --git a/src/mainboard/system76/rpl/variants/oryp11/data.vbt b/src/mainboard/system76/rpl/variants/oryp11/data.vbt Binary files differnew file mode 100644 index 0000000000..bc9a93124f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/data.vbt diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio.c b/src/mainboard/system76/rpl/variants/oryp11/gpio.c new file mode 100644 index 0000000000..74fbde85bc --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // PCH_LAN_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_GPO(GPD11, 1, DEEP), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0 + PAD_CFG_GPO(GPP_A6, 1, DEEP), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_CFG_GPO(GPP_A8, 1, DEEP), // GPP_A8 + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_CFG_GPO(GPP_A11, 1, DEEP), + PAD_CFG_GPO(GPP_A12, 1, DEEP), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + _PAD_CFG_STRUCT(GPP_A15, 0x86880100, 0x0000), // G_DP_A_HPD_L + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + _PAD_CFG_STRUCT(GPP_A18, 0x86880100, 0x0000), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPO(GPP_A20, 1, DEEP), // DGPU_OVRM + PAD_CFG_GPO(GPP_A21, 1, DEEP), // GPIO_LANRTD3 + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_PCH) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + _PAD_CFG_STRUCT(GPP_B5, 0x44000a01, 0x0000), // GPPB_I2C2_SDA + _PAD_CFG_STRUCT(GPP_B6, 0x44000a01, 0x0000), // GPPB_I2C2_SCL + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), // GPP_B11 + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // SYS_RESET# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // GPP_B14 + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18 + PAD_CFG_GPO(GPP_B19, 1, DEEP), + PAD_CFG_GPO(GPP_B20, 1, DEEP), + PAD_CFG_GPO(GPP_B21, 1, DEEP), + PAD_CFG_GPO(GPP_B22, 1, DEEP), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23 + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_SSD1_PWR_EN + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5 + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPO(GPP_D4, 0, DEEP), // PS8461_SW + // GPP_D5 (PEX_SSD2_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D6, 1, DEEP), + // GPP_D7 (WLAN_CLKREQ#) configured by FSP + // GPP_D8 (PEG_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D9, 1, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), // GPP_D10 + _PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x3c00), + PAD_CFG_GPO(GPP_D12, 0, DEEP), // GPP_D12 + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_W AKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_SSD2_PWR_EN + PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D19, 1, DEEP), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_W AKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + PAD_CFG_GPO(GPP_E5, 0, DEEP), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6 + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPO(GPP_E10, 1, DEEP), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_E12, 1, DEEP), + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD + PAD_CFG_GPO(GPP_E15, 1, DEEP), // CCD_FW_WP# + PAD_CFG_GPO(GPP_E16, 1, DEEP), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NATIVE), // GPP_E18_TBT_LSX0_TXD + PAD_NC(GPP_E19, NATIVE), // GPP_E19_TBT_LSX0_RXD + PAD_CFG_GPO(GPP_E20, 1, DEEP), + PAD_CFG_GPO(GPP_E21, 0, DEEP), // GPP_E21 + PAD_CFG_GPO(GPP_E22, 1, DEEP), + PAD_CFG_GPO(GPP_E23, 1, DEEP), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST# + // GPP_F5 (XTAL_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST# + PAD_CFG_GPO(GPP_F8, 1, DEEP), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_CFG_GPO(GPP_F10, 0, DEEP), // GPP_F10 + PAD_CFG_GPO(GPP_F11, 1, DEEP), + PAD_CFG_GPI(GPP_F12, NONE, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_F14, 1, DEEP), + PAD_CFG_GPO(GPP_F15, 1, DEEP), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_CFG_GPO(GPP_F17, 1, DEEP), + PAD_CFG_GPO(GPP_F18, 1, DEEP), + // GPP_F19 (LAN_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST# + PAD_CFG_GPO(GPP_F21, 1, DEEP), + PAD_CFG_GPO(GPP_F22, 1, DEEP), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), // GPP_H0 + PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M2_SSD1_RST# + PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M2_WLAN_RST# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RXD) configured in bootblock + // GPP_H11 (UART0_TXD) configured in bootblock + PAD_CFG_GPO(GPP_H12, 1, DEEP), + PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H15, 1, DEEP), + PAD_CFG_GPO(GPP_H16, 1, DEEP), + PAD_CFG_GPO(GPP_H17, 1, DEEP), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // PEX_SSD1_CLKREQ# + PAD_CFG_GPI(GPP_H20, NONE, DEEP), + PAD_CFG_GPI(GPP_H21, NONE, DEEP), + PAD_CFG_GPO(GPP_H22, 0, DEEP), + // GPP_H23 (CARD_CLKREQ#) configured by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_CFG_GPO(GPP_R5, 1, DEEP), + PAD_CFG_GPO(GPP_R6, 1, DEEP), + PAD_CFG_GPO(GPP_R7, 1, DEEP), + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPO(GPP_S0, 1, DEEP), + PAD_CFG_GPO(GPP_S1, 1, DEEP), + PAD_CFG_GPO(GPP_S2, 1, DEEP), + PAD_CFG_GPO(GPP_S3, 1, DEEP), + PAD_CFG_GPO(GPP_S4, 1, DEEP), + PAD_CFG_GPO(GPP_S5, 1, DEEP), + PAD_CFG_GPO(GPP_S6, 1, DEEP), + PAD_CFG_GPO(GPP_S7, 1, DEEP), + + /* ------- GPIO Group GPP_T ------- */ + PAD_CFG_GPO(GPP_T2, 1, DEEP), + PAD_CFG_GPO(GPP_T3, 1, DEEP), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c new file mode 100644 index 0000000000..85b9307d45 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c new file mode 100644 index 0000000000..dbed36fe24 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155866a2, /* Subsystem ID */ + 243, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + AZALIA_SUBVENDOR(0, 0x155866a2), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60120), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + // ALC1318 smart amp + 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, + 0x02050058, 0x02048ed1, 0x02050063, 0x0204e430, + 0x02050016, 0x02048020, 0x02050016, 0x02048020, + 0x02050043, 0x02043005, 0x02050058, 0x02048ed1, + 0x02050063, 0x0204e430, 0x05b50000, 0x05b43530, + 0x05750002, 0x05741400, 0x05b5000a, 0x05b45520, + 0x02050042, 0x020486cb, 0x0143b000, 0x01470740, + 0x02050036, 0x02042a6a, 0x02050008, 0x0204800b, + 0x02050007, 0x020403c3, 0x01470c02, 0x01470c02, + 0x00c37100, 0x01b3b000, 0x01b70740, 0x00b37417, + 0x0205001b, 0x02044002, 0x0205001b, 0x02044002, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c000, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f20d, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f212, 0x0205002b, 0x0204003e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c001, + 0x0205002b, 0x02040002, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c003, 0x0205002b, 0x02040022, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c004, + 0x0205002b, 0x02040044, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c005, 0x0205002b, 0x02040044, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c007, + 0x0205002b, 0x02040064, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c00e, 0x0205002b, 0x020400e7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f223, + 0x0205002b, 0x0204007f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f224, 0x0205002b, 0x020400db, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f225, + 0x0205002b, 0x020400ee, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f226, 0x0205002b, 0x0204003f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f227, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f21a, 0x0205002b, 0x02040078, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f242, + 0x0205002b, 0x0204003c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c120, 0x0205002b, 0x02040040, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c321, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c200, + 0x0205002b, 0x020400d8, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c201, 0x0205002b, 0x02040027, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c202, + 0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c400, 0x0205002b, 0x0204000e, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c401, + 0x0205002b, 0x02040043, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c402, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c403, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c404, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c406, + 0x0205002b, 0x02040040, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c407, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c408, + 0x0205002b, 0x0204003f, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c300, 0x0205002b, 0x02040001, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c125, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df00, 0x0205002b, 0x02040010, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204df5f, + 0x0205002b, 0x02040001, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204df60, 0x0205002b, 0x020400a7, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ea00, + 0x0205002b, 0x02040047, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c203, 0x0205002b, 0x02040084, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c206, + 0x0205002b, 0x02040078, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040003, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x020400e0, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f102, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f103, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f104, 0x0205002b, 0x020400f4, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f105, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f109, 0x0205002b, 0x02040065, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10a, + 0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e706, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e707, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e806, 0x0205002b, 0x0204000f, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204e807, + 0x0205002b, 0x02040030, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204ce07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf04, 0x0205002b, 0x02040002, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf05, + 0x0205002b, 0x02040087, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204cf06, 0x0205002b, 0x020400a2, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204cf07, + 0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204ce60, 0x0205002b, 0x020400e3, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204c130, + 0x0205002b, 0x02040051, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204e000, 0x0205002b, 0x020400a8, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040004, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02044100, 0x02050029, 0x02041888, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204c121, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f102, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f103, 0x0205002b, 0x02040000, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f104, + 0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f105, 0x0205002b, 0x02040023, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f109, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b, + 0x0205002c, 0x0204b423, 0x02050027, 0x02040010, + 0x02050028, 0x02040000, 0x02050029, 0x0204f10b, + 0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423, + 0x02050027, 0x02040010, 0x02050028, 0x02040000, + 0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c, + 0x0205002c, 0x0204b423, + + // XXX: Duplicate last 2 u32s to keep in 4-dword blocks + 0x0205002c, 0x0204b423, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb new file mode 100644 index 0000000000..8c5315ba67 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -0,0 +1,97 @@ +chip soc/intel/alderlake + device domain 0 on + subsystemid 0x1558 0x66a2 inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + end + device ref tcss_dma0 on end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # AJ_USB1: USB-A 3.2 Gen 1 (Left) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1: USB-C Thunderbolt (Right) + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1: USB-A 3.2 Gen 1 (Right) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB1: USB-A 3.2 Gen 1 (Left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1: USB-A 3.2 Gen 1 (Right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2: USB-C 3.2 Gen 2 (Back) + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # CPU PCIe RP#2 x8, Clock 3 (GPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie4_0 on + # CPU RP#1 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie4_1 on + # PCIE RP#3 x4, Clock 4 (SSD1) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp5 on + # PCH RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 on + # PCH RP#6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp7 on + # PCH RP#7 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + end +end diff --git a/src/mainboard/system76/rpl/variants/oryp11/romstage.c b/src/mainboard/system76/rpl/variants/oryp11/romstage.c new file mode 100644 index 0000000000..1e597c72a6 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} |