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-rw-r--r--src/mainboard/google/brya/romstage.c7
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c7
-rw-r--r--src/mainboard/intel/shadowmountain/romstage.c3
-rw-r--r--src/mainboard/prodrive/atlas/romstage_fsp_params.c3
4 files changed, 15 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c
index ae47167ec1..a00cf32a83 100644
--- a/src/mainboard/google/brya/romstage.c
+++ b/src/mainboard/google/brya/romstage.c
@@ -13,6 +13,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
const struct mb_cfg *mem_config = variant_memory_params();
bool half_populated = variant_is_half_populated();
struct mem_spd spd_info;
+ bool dimms_changed = false;
memset(&spd_info, 0, sizeof(spd_info));
variant_get_spd_info(&spd_info);
@@ -20,7 +21,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
const struct pad_config *pads;
size_t pads_num;
- memcfg_init(m_cfg, mem_config, &spd_info, half_populated);
+ memcfg_init(m_cfg, mem_config, &spd_info, half_populated, &dimms_changed);
+ if (dimms_changed) {
+ memupd->FspmArchUpd.NvsBufferPtr = 0;
+ memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
+ }
pads = variant_romstage_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index a0453efd5f..5b5cc6b295 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -48,6 +48,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
const struct mb_cfg *mem_config = variant_memory_params();
int board_id = get_board_id();
const bool half_populated = false;
+ bool dimms_changed = false;
const struct mem_spd memory_down_spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
@@ -72,7 +73,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
case ADL_P_DDR5_1:
- memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated);
+ memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated,
+ &dimms_changed);
break;
case ADL_P_DDR5_2:
case ADL_P_LP4_1:
@@ -82,7 +84,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
case ADL_M_LP4:
case ADL_M_LP5:
case ADL_N_LP5:
- memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated);
+ memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated,
+ &dimms_changed);
break;
default:
die("Unknown board id = 0x%x\n", board_id);
diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c
index 48c20db1ab..0951936bdc 100644
--- a/src/mainboard/intel/shadowmountain/romstage.c
+++ b/src/mainboard/intel/shadowmountain/romstage.c
@@ -12,11 +12,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
const struct mb_cfg *mem_config = variant_memory_params();
const bool half_populated = false;
+ bool dimms_changed = false;
const struct mem_spd lp5_spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = variant_memory_sku(),
};
- memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated);
+ memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated, &dimms_changed);
}
diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c
index 837a528422..9728a99a4f 100644
--- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c
+++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c
@@ -32,6 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
const struct mb_cfg *mem_config = &ddr5_mem_config;
const bool half_populated = false;
+ bool dimms_changed = false;
const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
@@ -47,5 +48,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
},
};
- memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated);
+ memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed);
}