diff options
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index bf66e4b70f..d67b2176ab 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -4,6 +4,48 @@ chip soc/intel/elkhartlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "Heci2Enable" = "1" + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # Enable All Root Ports (1-7) + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "0x00" + register "PcieClkSrcUsage[1]" = "0x06" + register "PcieClkSrcUsage[2]" = "0x04" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + + register "PcieClkSrcClkReq[0]" = "0x0" + register "PcieClkSrcClkReq[1]" = "0x1" + register "PcieClkSrcClkReq[2]" = "0x2" + register "PcieClkSrcClkReq[3]" = "0x3" + register "PcieClkSrcClkReq[4]" = "0x4" + register "PcieClkSrcClkReq[5]" = "0x5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |