summaryrefslogtreecommitdiff
path: root/src/mainboard/via
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/via')
-rw-r--r--src/mainboard/via/epia-cn/Config.lb135
-rw-r--r--src/mainboard/via/epia-cn/Options.lb98
-rw-r--r--src/mainboard/via/epia-m/Config.lb159
-rw-r--r--src/mainboard/via/epia-m/Options.lb135
-rw-r--r--src/mainboard/via/epia-m700/Config.lb165
-rw-r--r--src/mainboard/via/epia-m700/Options.lb138
-rw-r--r--src/mainboard/via/epia-n/Config.lb202
-rw-r--r--src/mainboard/via/epia-n/Options.lb113
-rw-r--r--src/mainboard/via/epia/Config.lb156
-rw-r--r--src/mainboard/via/epia/Options.lb143
-rw-r--r--src/mainboard/via/pc2500e/Config.lb161
-rw-r--r--src/mainboard/via/pc2500e/Options.lb109
-rw-r--r--src/mainboard/via/vt8454c/Config.lb163
-rw-r--r--src/mainboard/via/vt8454c/Options.lb233
14 files changed, 0 insertions, 2110 deletions
diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb
deleted file mode 100644
index 42d62cbacf..0000000000
--- a/src/mainboard/via/epia-cn/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
- object fadt.o
- object dsdt.o
- object acpi_tables.o
-end
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700 # Northbridge
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- device pci f.0 on end # IDE
- register "fn_ctrl_lo" = "0x80"
- register "fn_ctrl_hi" = "0x1d"
- device pci 10.0 on end # OHCI
- device pci 10.1 on end # OHCI
- device pci 10.2 on end # OHCI
- device pci 10.3 on end # OHCI
- device pci 10.4 on end # EHCI
- device pci 10.5 on end # UDCI
- device pci 11.0 on # Southbridge LPC
- chip superio/via/vt1211 # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
- end
- end
- device pci 11.5 on end # AC'97 audio
- # device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
- device apic_cluster 0 on # APIC cluster
- chip cpu/via/model_c7 # VIA C7
- device apic 0 on end # APIC
- end
- end
-end
diff --git a/src/mainboard/via/epia-cn/Options.lb b/src/mainboard/via/epia-cn/Options.lb
deleted file mode 100644
index 718c75d8fb..0000000000
--- a/src/mainboard/via/epia-cn/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-
-end
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
deleted file mode 100644
index 011ce5ad24..0000000000
--- a/src/mainboard/via/epia-m/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-object vgabios.o
-
-if CONFIG_GENERATE_ACPI_TABLES
- object fadt.o
- object dsdt.o
- object acpi_tables.o
-end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8623
-
- device apic_cluster 0 on
- chip cpu/via/model_c3
- device apic 0 on end
- end
- end
-
- device pci_domain 0 on
- chip southbridge/via/vt8235
-
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.3 on end # USB 2
-
- device pci 11.0 on # Southbridge
- chip superio/via/vt1211
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
-
- end
- end
-
- device pci 11.1 on end # IDE
- # 2-4 non existant?
- device pci 11.5 on end # AC97 Audio
- device pci 11.6 off end # AC97 Modem
- device pci 12.0 on end # Ethernet
- end
-# This is on the EPIA MII, not the M.
- chip southbridge/ricoh/rl5c476
- register "enable_cf" = "1"
- device pci 0a.0 on end
- device pci 0a.1 on end
- end
- end
-end
diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb
deleted file mode 100644
index 4583331f55..0000000000
--- a/src/mainboard/via/epia-m/Options.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_CONSOLE_VGA=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Use TSC for udelay.
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-
-
-##
-## Build code to load acpi tables
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_CONSOLE_SERIAL8250=1
-end
diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb
deleted file mode 100644
index d7d7cbedc8..0000000000
--- a/src/mainboard/via/epia-m700/Config.lb
+++ /dev/null
@@ -1,165 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 One Laptop per Child, Association, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-driver wakeup.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
- object fadt.o
- object dsdt.o
- # object ssdt.o
- object acpi_tables.o
-end
-# These lines maybe noused.
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-if CONFIG_USE_DCACHE_RAM
- if CONFIG_USE_INIT
- makerule ./cache_as_ram_auto.o
- depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
- end
- else
- makerule ./cache_as_ram_auto.inc
- depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
- action "perl -e 's/.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/.text/.section .rom.text/g' -pi $@"
- end
- end
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-ldscript /cpu/x86/16bit/entry16.lds
-
-mainboardinit northbridge/via/vx800/romstrap.inc
-ldscript /northbridge/via/vx800/romstrap.lds
-
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-# mainboardinit arch/i386/lib/cpu_reset.inc
-# Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c,
-# but cpu_reset.inc also has code to jump to __main() which is not included
-# in cache_as_ram_auto_auto.c.
-
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-if CONFIG_USE_DCACHE_RAM
- mainboardinit cpu/via/car/cache_as_ram.inc
-end
-
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- # failover.inc need definition in cpu_reset.inc, but we do not include
- # cpu_reset.inc,so ...
- # mainboardinit ./failover.inc
-end
-# mainboardinit cpu/x86/fpu_enable.inc
-
-if CONFIG_USE_DCACHE_RAM
- if CONFIG_USE_INIT
- initobject cache_as_ram_auto.o
- else
- mainboardinit ./cache_as_ram_auto.inc
- end
-end
-
-# mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-
-config chip.h
-
-chip northbridge/via/vx800 # Northbridge
- device pci_domain 0 on
- device pci 0.0 on end # Host Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # PCI to PCI Bridge
- device pci 0.4 on end # Power Management
- device pci 0.5 on end # APIC and Central Traffic Control
- device pci 0.6 on end # Scratch Registers
- device pci 0.7 on end # North-South Module Interface Control
- device pci 1.0 on end # PCI Bridge
- device pci f.0 on end # IDE/SATA
- # device pci f.1 on end # IDE
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.4 on end # USB 2.0
- device pci 11.0 on # Bus Control and Power Management (SB, LPC)
- chip superio/winbond/w83697hf
- # TODO: Check all devices, this may need some more work.
- device pnp 2e.0 off # Floppy (N/A?)
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port (N/A?)
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.6 off end # Consumer IR
- device pnp 2e.7 off end # Game port, GPIO 1
- device pnp 2e.8 off end # MIDI port, GPIO 5
- device pnp 2e.9 off end # GPIO 2-4
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HWM
- io 0x60 = 0x290
- end
- end
- end
- device pci 11.7 on end # North-South Module Interface Control
- device pci 14.0 on end # HD Audio (Azalia)
- end
- device apic_cluster 0 on # APIC cluster
- chip cpu/via/model_c7 # VIA C7
- device apic 0 on end # APIC
- end
- end
-end
diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb
deleted file mode 100644
index fffa5502d7..0000000000
--- a/src/mainboard/via/epia-m700/Options.lb
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 One Laptop per Child, Association, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-
-## New options
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-#uses MAX_RAM_SLOTS
-#uses USB_ENABLE
-#uses EHCI_ENABLE
-#uses HPET_ENABLE
-#uses USB_PORTNUM
-#uses FULL_ROM_SIZE
-#uses FULL_ROM_BASE
-#uses PAYLOAD_IS_SEABIOS
-#uses VIACONFIG_TOP_SM_SIZE_MB
-#uses VIACONFIG_VGA_PCI_10
-#uses VIACONFIG_VGA_PCI_14
-
-## New options
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xffef0000
-# default CONFIG_DCACHE_RAM_BASE = 0xffbf0000
-# default CONFIG_DCACHE_RAM_BASE = 0xfec00000 # HPET may use this.
-default CONFIG_DCACHE_RAM_SIZE = 8 * 1024
-default CONFIG_USE_INIT = 0
-#default MAX_RAM_SLOTS = 2
-#default USB_ENABLE = 1
-#default EHCI_ENABLE = 1
-#default HPET_ENABLE = 1
-#default USB_PORTNUM = 2
-#default FULL_ROM_SIZE = 512 * 1024
-#default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1)
-#default VIACONFIG_TOP_SM_SIZE_MB = 0
-# default VIACONFIG_VGA_PCI_10 = 0xd0000008
-# default VIACONFIG_VGA_PCI_14 = 0xfd000000
-#default VIACONFIG_VGA_PCI_10 = 0xf8000008
-#default VIACONFIG_VGA_PCI_14 = 0xfc000000
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 1
-
-# Define framebuffer size of VX800's integrated graphics card.
-# Supports: 32, 64, 128, 256.
-default CONFIG_VIDEO_MB = 64
-
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-# TODO: There is an irq_tables.c file, should it be used?
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_IRQ_SLOT_COUNT = 13
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 16 * 1024
-default CONFIG_HEAP_SIZE = 20 * 1024
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/via/epia-n/Config.lb b/src/mainboard/via/epia-n/Config.lb
deleted file mode 100644
index ac0ef8bde9..0000000000
--- a/src/mainboard/via/epia-n/Config.lb
+++ /dev/null
@@ -1,202 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-#object vgabios.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-#acpi_create_fadt is located in VT8237R code
- makerule dsdt.c
- depends "$(CONFIG_MAINBOARD)/dsdt.asl"
- action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
- action "mv dsdt.hex dsdt.c"
- end
- object ./dsdt.o
- object acpi_tables.o
-end
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn400 # Northbridge
-
- device apic_cluster 0 on # APIC cluster
- chip cpu/via/model_c3 # VIA C3
- device apic 0 on end # APIC
- end
- end
-
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- device pci f.0 on end # IDE/SATA
- device pci f.1 on end # IDE
- register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97
- register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating
- device pci 10.0 on end # OHCI
- device pci 10.1 on end # OHCI
- device pci 10.2 on end # OHCI
- device pci 10.3 on end # OHCI
- device pci 10.4 on end # EHCI
- device pci 10.5 off end # USB Direct
- device pci 11.0 on # Southbridge LPC
- chip superio/winbond/w83697hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.6 off # IR Port
- io 0x60 = 0x000
- end
- device pnp 2e.7 off # GPIO 1
- io 0x60 = 0x201 # 0x201
- end
- device pnp 2e.8 off # GPIO 5
- io 0x60 = 0x330 # 0x330
- end
- device pnp 2e.9 off # GPIO 2, 3,and 4
- io 0x60 = 0x000 #
- end
- device pnp 2e.a off # ACPI
- io 0x60 = 0x000 #
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 11.5 off end # AC'97 audio
- device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
-end
diff --git a/src/mainboard/via/epia-n/Options.lb b/src/mainboard/via/epia-n/Options.lb
deleted file mode 100644
index 416b8128d9..0000000000
--- a/src/mainboard/via/epia-n/Options.lb
+++ /dev/null
@@ -1,113 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_RAMTOP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_SMP
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-uses CONFIG_COMPRESS
-uses CONFIG_EPIA_VT8237R_INIT
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_EPIA_VT8237R_INIT = 1
-#default CONFIG_RAMTOP = 4 * 1024*1024
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_COMPRESS = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 64
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FAILOVER_BOOT = 0
-default CONFIG_USE_FAILOVER_IMAGE = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_SMP = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-#default CONFIG_MAINBOARD = "EPIA-N"
-default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
-
-end
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
deleted file mode 100644
index c75c21e060..0000000000
--- a/src/mainboard/via/epia/Config.lb
+++ /dev/null
@@ -1,156 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8601
- device pci_domain 0 on
- device pci 0.0 on end # Northbridge
-# device pci 0.1 on # AGP bridge
- # device pci 0.0 on end # Integrated VGA
-# end
- chip southbridge/via/vt8231
- register "enable_native_ide" = "0"
- register "enable_com_ports" = "1"
- register "enable_keyboard" = "0"
- device pci 11.0 on # Southbrdge
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- register "com1" = "{CONFIG_TTYS0_BAUD}"
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
- device pci 11.1 on end # Ide
- device pci 11.2 off end # Usb port 0-1
- device pci 11.3 off end # Usb port 2-3
- device pci 11.4 off end # ACPI
- device pci 11.5 off end # AC97 Audio
- device pci 11.6 on end # AC97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
-
- device apic_cluster 0 on
- chip cpu/via/model_c3
- device apic 0 on end
- end
- end
-end
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
deleted file mode 100644
index 466ffcc382..0000000000
--- a/src/mainboard/via/epia/Options.lb
+++ /dev/null
@@ -1,143 +0,0 @@
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_UDELAY_IO
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-
-default CONFIG_CONSOLE_SERIAL8250=1
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## use io based udelay function
-## disable IO and enable TSC on Nehemiah boards
-##
-default CONFIG_UDELAY_IO=1
-default CONFIG_UDELAY_TSC=0
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-end
diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb
deleted file mode 100644
index 01c226670e..0000000000
--- a/src/mainboard/via/pc2500e/Config.lb
+++ /dev/null
@@ -1,161 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
- object fadt.o
- object dsdt.o
- object acpi_tables.o
-end
-makerule ./failover.E
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700 # Northbridge
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- device pci f.0 on end # SATA
- device pci f.1 on end # IDE
- register "fn_ctrl_lo" = "0x80"
- register "fn_ctrl_hi" = "0x1d"
- device pci 10.0 on end # UHCI
- device pci 10.1 on end # UHCI
- device pci 10.2 on end # UHCI
- device pci 10.3 on end # UHCI
- device pci 10.4 on end # EHCI
- device pci 10.5 on end # UDCI
- device pci 11.0 on # Southbridge LPC
- chip superio/ite/it8716f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # COM2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x0000
- irq 0x70 = 9
- end
- device pnp 2e.5 off # PS/2 keyboard (not used)
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 off # PS/2 mouse (not used)
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO
- io 0x60 = 0x0000
- io 0x62 = 0x0800
- io 0x64 = 0x0000
- end
- device pnp 2e.8 off # MIDI port (N/A)
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 off # Game port (N/A)
- io 0x60 = 0x201
- end
- device pnp 2e.a on # Consumer IR
- io 0x60 = 0x310
- irq 0x70 = 11
- end
- end
- end
- device pci 11.5 on end # AC'97 audio
- # device pci 11.6 off end # AC'97 modem (N/A)
- device pci 12.0 on end # Ethernet
- end
- end
- device apic_cluster 0 on # APIC cluster
- chip cpu/via/model_c7 # VIA C7
- device apic 0 on end # APIC
- end
- end
-end
diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb
deleted file mode 100644
index 9e4896050b..0000000000
--- a/src/mainboard/via/pc2500e/Options.lb
+++ /dev/null
@@ -1,109 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-uses CONFIG_SMP
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_VIDEO_MB
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_SMP = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 10
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_MAINBOARD_VENDOR = "VIA"
-default CONFIG_MAINBOARD_PART_NUMBER = "pc2500e"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 1
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-end
diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb
deleted file mode 100644
index 6faa33c3b2..0000000000
--- a/src/mainboard/via/vt8454c/Config.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_MP_TABLE
- object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
- object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
- object fadt.o
- object acpi_tables.o
- makerule dsdt.c
- depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
- action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
- action "mv dsdt.hex dsdt.c"
- end
- object ./dsdt.o
-end
-
-##
-## Romcc output
-##
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
- action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-mainboardinit cpu/via/car/cache_as_ram.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/cx700
- device apic_cluster 0 on
- chip cpu/via/model_c7
- device apic 0 on end
- end
- end
- device pci_domain 0 on
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on # PCI Bridge
- device pci 0.0 on end # Onboard Video
- end # PCI Bridge
- device pci f.0 on end # IDE/SATA
- #device pci f.1 on end # IDE
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.4 on end # USB 2.0
- device pci 11.0 on # Southbridge LPC
- chip superio/via/vt1211
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
- end # superio
- end # pci 11.0
- # 1-4 non existant
- #device pci 11.5 on end # AC97 Audio
- #device pci 11.6 off end # AC97 Modem
- #device pci 12.0 on end # Ethernet
- end # pci domain 0
-end # cx700
-
diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb
deleted file mode 100644
index cb796caf97..0000000000
--- a/src/mainboard/via/vt8454c/Options.lb
+++ /dev/null
@@ -1,233 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_HAVE_LOW_TABLES
-
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-# compiler specifics
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# Console specifics
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_SMP
-uses CONFIG_IOAPIC
-
-uses CONFIG_GDB_STUB
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256*1024
-
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xffef0000
-#default CONFIG_DCACHE_RAM_BASE=0xffbf0000
-#default CONFIG_DCACHE_RAM_BASE=0xfec00000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-###
-### Leave this to 0; VGA is handled by seperate code.
-###
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_CONSOLE_VGA=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Use TSC for udelay.
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to load acpi tables
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Build code to fill in tables both in low and high memory
-##
-default CONFIG_HAVE_LOW_TABLES=1
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_SMP=1
-default CONFIG_IOAPIC=1
-
-###
-### LinuxBIOS layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-## Select the coreboot loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## CONFIG_DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-end
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 20:19:27 +0000