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-rw-r--r--src/mainboard/prodrive/atlas/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index c90c69c4f6..86e86f5455 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -96,7 +96,7 @@ chip soc/intel/alderlake
}"
register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
- # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
+ # Enable CPU PCIE RP 1, 2, 3 using free running CLK (0x80)
# Clock source is shared hence marked as free running.
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,