diff options
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/dsdt.dsl')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/dsdt.dsl | 303 |
1 files changed, 303 insertions, 0 deletions
diff --git a/src/mainboard/kontron/986lcd-m/dsdt.dsl b/src/mainboard/kontron/986lcd-m/dsdt.dsl new file mode 100644 index 0000000000..95627fb45d --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/dsdt.dsl @@ -0,0 +1,303 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "986LCD", "COREBOOT", 0x0000001) +{ + Scope (\_PR) + { + Processor (CPU1, 0x01, 0x00000810, 0x06) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Scope (\_PR) + { + Processor (CPU2, 0x02, 0x00000000, 0x00) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Name (PICM, 0x00) + Method (_PIC, 1, NotSerialized) + { + Store (Arg0, PICM) + } + + Scope (\_SB) + { + Name (PR00, Package (0x12) + { + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x03, LNKA, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 } 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