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-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c61
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h75
2 files changed, 30 insertions, 106 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index d2d9202f8f..73f5c2ccfb 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include "PlatformGnbPcieComplex.h"
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -25,65 +24,65 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
- GNB_GPP_PORT4_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
4,
- GNB_GPP_PORT4_HOTPLUG_SUPPORT,
- GNB_GPP_PORT4_SPEED_MODE,
- GNB_GPP_PORT4_SPEED_MODE,
- GNB_GPP_PORT4_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
- GNB_GPP_PORT5_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
5,
- GNB_GPP_PORT5_HOTPLUG_SUPPORT,
- GNB_GPP_PORT5_SPEED_MODE,
- GNB_GPP_PORT5_SPEED_MODE,
- GNB_GPP_PORT5_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
- GNB_GPP_PORT6_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
6,
- GNB_GPP_PORT6_HOTPLUG_SUPPORT,
- GNB_GPP_PORT6_SPEED_MODE,
- GNB_GPP_PORT6_SPEED_MODE,
- GNB_GPP_PORT6_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
46)
},
/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
- GNB_GPP_PORT7_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled,
+ ChannelTypeExt6db,
7,
- GNB_GPP_PORT7_HOTPLUG_SUPPORT,
- GNB_GPP_PORT7_SPEED_MODE,
- GNB_GPP_PORT7_SPEED_MODE,
- GNB_GPP_PORT7_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
0)
},
/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
- GNB_GPP_PORT8_CHANNEL_TYPE,
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled,
+ ChannelTypeExt6db,
8,
- GNB_GPP_PORT8_HOTPLUG_SUPPORT,
- GNB_GPP_PORT8_SPEED_MODE,
- GNB_GPP_PORT8_SPEED_MODE,
- GNB_GPP_PORT8_LINK_ASPM,
+ HotplugDisabled,
+ PcieGen2,
+ PcieGen2,
+ AspmL0sL1,
0)
}
};
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
deleted file mode 100644
index 782f5c234a..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
-#define _PLATFORM_GNB_PCIE_COMPLEX_H
-
-/**
- * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
- *
- * GNB_GPP_PORT?_PORT_PRESENT
- * 0:Disable 1:Enable
- *
- * GNB_GPP_PORT?_SPEED_MODE
- * 0:Auto 1:GEN1 2:GEN2
- *
- * GNB_GPP_PORT?_LINK_ASPM
- * 0:Disable 1:L0s 2:L1 3:L0s+L1
- *
- * GNB_GPP_PORT?_CHANNEL_TYPE -
- * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
- *
- * GNB_GPP_PORT?_HOTPLUG_SUPPORT
- * 0:Disable 1:Basic 3:Enhanced
- */
-
-/* GNB GPP 4 */
-#define GNB_GPP_PORT4_PORT_PRESENT 1
-#define GNB_GPP_PORT4_SPEED_MODE 2
-#define GNB_GPP_PORT4_LINK_ASPM 3
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
-
-/* GNB GPP 5 */
-#define GNB_GPP_PORT5_PORT_PRESENT 1
-#define GNB_GPP_PORT5_SPEED_MODE 2
-#define GNB_GPP_PORT5_LINK_ASPM 3
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
-
-/* GNB GPP 6 */
-#define GNB_GPP_PORT6_PORT_PRESENT 1
-#define GNB_GPP_PORT6_SPEED_MODE 2
-#define GNB_GPP_PORT6_LINK_ASPM 3
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
-
-/* GNB GPP 7 */
-#define GNB_GPP_PORT7_PORT_PRESENT 0
-#define GNB_GPP_PORT7_SPEED_MODE 2
-#define GNB_GPP_PORT7_LINK_ASPM 3
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
-
-/* GNB GPP 8 */
-#define GNB_GPP_PORT8_PORT_PRESENT 1
-#define GNB_GPP_PORT8_SPEED_MODE 2
-#define GNB_GPP_PORT8_LINK_ASPM 3
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
-
-#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
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