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-rw-r--r--src/mainboard/intel/dcp847ske/early_southbridge.c10
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c3
2 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 705ace9bc6..984629574c 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,18 +27,8 @@
#include "superio.h"
#include "thermal.h"
-#if CONFIG(DISABLE_UART_ON_TESTPADS)
-#define DEBUG_UART_EN 0
-#else
-#define DEBUG_UART_EN COMA_LPC_EN
-#endif
-
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
- CNF2_LPC_EN | DEBUG_UART_EN);
- /* Decode SuperIO 0x0a00 */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index ee3cec1ebf..d56576e2e5 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -32,9 +32,6 @@ void pch_enable_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
- /* Set COM1/COM2 decode range */
- pci_write_config16(dev, LPC_IO_DEC, 0x0010);
-
/* Enable SuperIO + PS/2 Keyboard/Mouse */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);