diff options
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b84fddc397..0e34eb2663 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fcadcee990..17af01aaeb 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -13,7 +13,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" |