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-rw-r--r--src/mainboard/intel/adlrvp/devicetree_m.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 2c50c289e5..5d24a420c7 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -27,6 +27,9 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
+ # Enable HECI1 communication
+ register "HeciEnabled" = "1"
+
# FSP configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1