diff options
Diffstat (limited to 'src/mainboard/intel/icelake_rvp')
28 files changed, 0 insertions, 2271 deletions
diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig deleted file mode 100644 index 24a15bed5d..0000000000 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ /dev/null @@ -1,52 +0,0 @@ -if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select EC_ACPI - select HAVE_SPD_IN_CBFS - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS - select HAVE_SPD_IN_CBFS - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_ICELAKE - select MAINBOARD_USES_IFD_EC_REGION - select INTEL_LPSS_UART_FOR_CONSOLE - -config MAINBOARD_DIR - default "intel/icelake_rvp" - -config VARIANT_DIR - default "icl_u" if BOARD_INTEL_ICELAKE_RVPU - default "icl_y" if BOARD_INTEL_ICELAKE_RVPY - -config MAINBOARD_PART_NUMBER - default "Icelake RVP" - -config MAINBOARD_FAMILY - string - default "Intel_icelake_rvp" - -config MAX_CPUS - int - default 8 - -config DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config DIMM_SPD_SIZE - default 512 - -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA - -config UART_FOR_CONSOLE - int - default 2 -endif diff --git a/src/mainboard/intel/icelake_rvp/Kconfig.name b/src/mainboard/intel/icelake_rvp/Kconfig.name deleted file mode 100644 index 9ba17a65be..0000000000 --- a/src/mainboard/intel/icelake_rvp/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -config BOARD_INTEL_ICELAKE_RVPU - bool "Icelake U DDR4/LPDDR4 RVP" -config BOARD_INTEL_ICELAKE_RVPY - bool "Icelake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc deleted file mode 100644 index 60551c5213..0000000000 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -subdirs-y += spd - -bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c - -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += romstage_fsp_params.c -romstage-y += board_id.c - -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c -ramstage-y += mainboard.c -ramstage-y += board_id.c - -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - -subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c deleted file mode 100644 index 0ab7e6a5e9..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_id.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include "board_id.h" -#include <boardid.h> -#include <ec/acpi/ec.h> -#include <stdint.h> -#include <ec/google/chromeec/ec.h> - -static int get_board_id_via_ext_ec(void) -{ - uint32_t id = BOARD_ID_INIT; - - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - - return id; -} - -/* Get Board ID via EC I/O port write/read */ -int get_board_id(void) -{ - MAYBE_STATIC_NONZERO int id = -1; - - if (id < 0) { - if (CONFIG(EC_GOOGLE_CHROMEEC)) - id = get_board_id_via_ext_ec(); - else{ - uint8_t buffer[2]; - uint8_t index; - if (send_ec_command(EC_FAB_ID_CMD) == 0) { - for (index = 0; index < sizeof(buffer); index++) - buffer[index] = recv_ec_data(); - id = (buffer[0] << 8) | buffer[1]; - } - } - } - - return id; -} diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h deleted file mode 100644 index 46314755a1..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_id.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_BOARD_ID_H_ -#define _MAINBOARD_BOARD_ID_H_ - -/* Board/FAB ID Command */ -#define EC_FAB_ID_CMD 0x0D - -/* - * Returns board information (board id[15:8] and - * Fab info[7:0]) on success and < 0 on error - */ -int get_board_id(void); - -#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/icelake_rvp/board_info.txt b/src/mainboard/intel/icelake_rvp/board_info.txt deleted file mode 100644 index 48ec997d1b..0000000000 --- a/src/mainboard/intel/icelake_rvp/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Intel -Board name: Icelake rvp -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c deleted file mode 100644 index d7f3255974..0000000000 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <bootblock_common.h> -#include <soc/gpio.h> - -void bootblock_mainboard_early_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c deleted file mode 100644 index f848234087..0000000000 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <bootmode.h> -#include <boot/coreboot_tables.h> -#include <gpio.h> -#include <types.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd deleted file mode 100644 index f4db8b4bc7..0000000000 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ /dev/null @@ -1,44 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { - SI_DESC@0x0 0x1000 - SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 - } - SI_BIOS@0x400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 - } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 - } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 - RW_LEGACY(CBFS)@0x610000 0x1c0000 - WP_RO@0x7d0000 0x430000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 - } - } - } -} diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl deleted file mode 100644 index 5a53226d25..0000000000 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <baseboard/ec.h> -#include <baseboard/gpio.h> - -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include <soc/intel/common/block/acpi/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - - // CPU - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/icelake/acpi/southbridge.asl> - } - } - -#if CONFIG(EC_GOOGLE_CHROMEEC) - /* ChromeOS Embedded Controller */ - Scope (\_SB.PCI0.LPCB) - { - /* ACPI code for EC SuperIO functions */ - #include <ec/google/chromeec/acpi/superio.asl> - /* ACPI code for EC functions */ - #include <ec/google/chromeec/acpi/ec.asl> - } -#endif - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c deleted file mode 100644 index 79f9a1fcce..0000000000 --- a/src/mainboard/intel/icelake_rvp/hda_verb.c +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/hda_verb.h> diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c deleted file mode 100644 index beb5b590c2..0000000000 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <device/device.h> -#include <soc/gpio.h> - -static void mainboard_init(void *chip_info) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, -}; diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c deleted file mode 100644 index 160f0a53ff..0000000000 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <fsp/api.h> -#include <soc/romstage.h> -#include <spd_bin.h> -#include "board_id.h" -#include "spd/spd.h" - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - u8 spd_index = (get_board_id() & 0x1F) & 0x7; - printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); - - if (spd_index > 0 && spd_index != 2) { - mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); - if (!mem_cfg->MemorySpdPtr00) - die("spd.bin not found\n"); - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - - mem_cfg->SpdAddressTable[0] = 0x0; - mem_cfg->SpdAddressTable[1] = 0x0; - mem_cfg->SpdAddressTable[2] = 0x0; - mem_cfg->SpdAddressTable[3] = 0x0; - } else { - mem_cfg->MemorySpdPtr00 = 0; - mem_cfg->MemorySpdPtr01 = 0; - mem_cfg->MemorySpdPtr10 = 0; - mem_cfg->MemorySpdPtr11 = 0; - - mem_cfg->SpdAddressTable[0] = 0xA0; - mem_cfg->SpdAddressTable[1] = 0xA2; - mem_cfg->SpdAddressTable[2] = 0xA4; - mem_cfg->SpdAddressTable[3] = 0xA6; - } - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); -} diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc deleted file mode 100644 index 8e3ce25085..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -romstage-y += spd_util.c - -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 -SPD_SOURCES += empty # 2b010 -SPD_SOURCES += empty # 3b011 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 4b100 -SPD_SOURCES += empty # 5b101 -SPD_SOURCES += samsung_K4F6E304HBMGCJ # 6b110 -SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex b/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex deleted file mode 100644 index 67b46cd239..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex b/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex deleted file mode 100644 index 62dff16182..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 10 0E 15 19 94 08 00 40 00 00 0A 22 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/icelake_rvp/spd/spd.h b/src/mainboard/intel/icelake_rvp/spd/spd.h deleted file mode 100644 index 978f01daa5..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/spd.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr); -void mainboard_fill_dq_map_ch1(void *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -#endif diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c deleted file mode 100644 index 39dd65a730..0000000000 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/cpu.h> -#include <intelblocks/mp_init.h> -#include <stdint.h> -#include <string.h> - -#include "../board_id.h" -#include "spd.h" - -enum icl_dimm_type { - icl_u_ddr4 = 0, - icl_u_lpddr4 = 1, - icl_u_lpddr4_type_3 = 4, - icl_y_lpddr4 = 6 -}; - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(void *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -static uint8_t get_spd_index(void) -{ - uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; - - return spd_index; -} - -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case icl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case icl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case icl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); - break; - case icl_u_lpddr4: - case icl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case icl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); - break; - default: - break; - } -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget_DDR4[5] = { - 100, 33, 32, 33, 28 }; - static const u16 RcompTarget_LPDDR4_Ax[5] = { - 80, 40, 40, 40, 30 }; - static const u16 RcompTarget_LPDDR4_Bx[5] = { - 60, 20, 20, 20, 20 }; - - switch (get_spd_index()) { - case icl_u_ddr4: - memcpy(rcomp_strength_ptr, RcompTarget_DDR4, - sizeof(RcompTarget_DDR4)); - break; - case icl_y_lpddr4: - case icl_u_lpddr4: - case icl_u_lpddr4_type_3: - if (cpu_get_cpuid() == CPUID_ICELAKE_A0) - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, - sizeof(RcompTarget_LPDDR4_Ax)); - else - memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx, - sizeof(RcompTarget_LPDDR4_Bx)); - break; - default: - break; - } -} diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index f05cb7722a..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index de0adf6cff..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h deleted file mode 100644 index 7233250105..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/hda_verb.h +++ /dev/null @@ -1,687 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* ALC 700 */ - 0x10EC0700, - 0xFFFFFFFF, - 0x00000023, - - AZALIA_SUBVENDOR(0, 0x10EC10F2), - AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x411111F0), - AZALIA_PIN_CFG(0, 0x15, 0x411111F0), - AZALIA_PIN_CFG(0, 0x16, 0x411111F0), - AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111F0), - AZALIA_PIN_CFG(0, 0x19, 0x04A11030), - AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1D, 0x40622005), - AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), - AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), - AZALIA_PIN_CFG(0, 0x21, 0x04211020), - AZALIA_PIN_CFG(0, 0x29, 0x411111F0), - - /* Widget node 0x20 */ - 0x02050045, - 0x02045289, - 0x0205004A, - 0x0204201B, - /* Widget node 0x20 - 1 */ - 0x05850000, - 0x05843888, - 0x0205006F, - 0x02042C0B, - - //Widget node 0X20 for ALC1305 20160603 update - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040320, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040039, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003B, - 0x02050028, - 0x0204FFFF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02041DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C0, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C1, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C2, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C3, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C4, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C5, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C6, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C7, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C8, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C9, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CA, - 0x02050028, - 0x020401FA, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CB, - 0x02050028, - 0x0204DE23, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CC, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CD, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CE, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CF, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D0, - 0x02050028, - 0x020403F5, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D1, - 0x02050028, - 0x0204AF1B, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D2, - 0x02050028, - 0x02041E0A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D3, - 0x02050028, - 0x0204368E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040040, - 0x02050028, - 0x0204800F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040062, - 0x02050028, - 0x02048000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040063, - 0x02050028, - 0x02044848, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040064, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040065, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040066, - 0x02050028, - 0x02044004, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040067, - 0x02050028, - 0x02040802, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040068, - 0x02050028, - 0x0204890F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040069, - 0x02050028, - 0x0204E021, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040070, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040071, - 0x02050000, - 0x02043330, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040072, - 0x02050000, - 0x02043333, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040073, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040074, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040075, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040076, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040050, - 0x02050028, - 0x020402EC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040051, - 0x02050028, - 0x02044909, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040052, - 0x02050028, - 0x020440B0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040046, - 0x02050028, - 0x0204C22E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040047, - 0x02050028, - 0x02040C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040048, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040049, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004A, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004B, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204721F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204009E, - 0x02050028, - 0x02040001, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024 -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 48d6c1c738..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include <soc/gpio.h> - -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc deleted file mode 100644 index 9f8b7815b5..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb deleted file mode 100644 index c00502a258..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ /dev/null @@ -1,345 +0,0 @@ -chip soc/intel/icelake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "SdCardPowerEnableActiveHigh" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - - # Enable Pch iSCLK - register "pch_isclk" = "1" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "2" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "0xE" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable DPTF - register "dptf_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .gspi[1] = { - .speed_mhz = 1, - .early_init = 1, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 4"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/wifi/generic - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c deleted file mode 100644 index 160f0d3733..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* UART2 RX */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART2 TX */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc deleted file mode 100644 index 9f8b7815b5..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb deleted file mode 100644 index 0d36f13054..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ /dev/null @@ -1,345 +0,0 @@ -chip soc/intel/icelake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "SdCardPowerEnableActiveHigh" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - - # Enable Pch iSCLK - register "pch_isclk" = "1" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "0xC" - register "PcieClkSrcUsage[3]" = "0x70" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "2" - register "PcieClkSrcUsage[6]" = "0x80" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieClkSrcUsage[8]" = "0x80" - register "PcieClkSrcUsage[9]" = "0x80" - register "PcieClkSrcUsage[10]" = "0x80" - register "PcieClkSrcUsage[11]" = "0x80" - register "PcieClkSrcUsage[12]" = "0x80" - register "PcieClkSrcUsage[13]" = "0x80" - register "PcieClkSrcUsage[14]" = "0x80" - register "PcieClkSrcUsage[15]" = "0x80" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcClkReq[6]" = "6" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcClkReq[8]" = "8" - register "PcieClkSrcClkReq[9]" = "9" - register "PcieClkSrcClkReq[10]" = "10" - register "PcieClkSrcClkReq[11]" = "11" - register "PcieClkSrcClkReq[12]" = "12" - register "PcieClkSrcClkReq[13]" = "13" - register "PcieClkSrcClkReq[14]" = "14" - register "PcieClkSrcClkReq[15]" = "15" - - register "SataEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" - register "SataPortsDevSlp[3]" = "1" - register "SataPortsDevSlp[4]" = "1" - register "SataPortsDevSlp[5]" = "1" - register "SataPortsDevSlp[6]" = "1" - register "SataPortsDevSlp[7]" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 1, - [PchSerialIoIndexGSPI1] = 1, - [PchSerialIoIndexGSPI2] = 1, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, - }" - - # Enable DPTF - register "dptf_enable" = "1" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .gspi[1] = { - .speed_mhz = 1, - .early_init = 1, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3-2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3-2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Port Unused 1"" - register "type" = "UPC_TYPE_UNUSED" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Port Unused 2"" - register "type" = "UPC_TYPE_UNUSED" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0000"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on - chip drivers/wifi/generic - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c deleted file mode 100644 index 160f0d3733..0000000000 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { -/* I2S2_SCLK */ -PAD_CFG_GPI(GPP_A7, NONE, PLTRST), -/* I2S2_RXD */ -PAD_CFG_GPI(GPP_A10, NONE, PLTRST), -/* TCH_PNL2_RST_N */ -PAD_CFG_GPO(GPP_A13, 1, DEEP), -/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ -PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* TCH_PNL2_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), -/* TC_RETIMER_FORCE_PWR */ -PAD_CFG_GPO(GPP_B4, 0, DEEP), -/* FPS_RST_N */ -PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* WIFI_RF_KILL_N */ -PAD_CFG_GPO(GPP_B15, 1, PLTRST), -/* M2_SSD_PWREN_N */ -PAD_CFG_GPO(GPP_B16, 1, DEEP), -/* WWAN_PERST_N */ -PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* BT_RF_KILL_N */ -PAD_CFG_GPO(GPP_B18, 1, PLTRST), -/* CRD_CAM_PWREN_1 */ -PAD_CFG_GPO(GPP_B23, 1, PLTRST), -/* WF_CAM_CLK_EN */ -PAD_CFG_GPO(GPP_C2, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ -PAD_CFG_GPO(GPP_C5, 1, DEEP), -/* TCH_PAD_INT_N */ -PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), -/* WWAN_RST_N */ -PAD_CFG_GPO(GPP_C10, 1, DEEP), -/* WWAN_FCP_OFF_N */ -PAD_CFG_GPO(GPP_C11, 1, DEEP), -/* CODEC_INT_N */ -PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), -/* SPKR_PD_N */ -PAD_CFG_GPO(GPP_C13, 1, PLTRST), -/* WF_CAM_RST_N */ -PAD_CFG_GPO(GPP_C15, 1, PLTRST), -/* CRD_CAM_STROBE_1 */ -PAD_CFG_GPO(GPP_C22, 0, PLTRST), -/* CRD_CAM_PRIVACY_LED_1 */ -PAD_CFG_GPO(GPP_C23, 0, PLTRST), -/* FLASH_DES_SEC_OVERRIDEs */ -PAD_CFG_GPO(GPP_D13, 0, DEEP), -/* TCH_PAD_LS_EN */ -PAD_CFG_GPO(GPP_D14, 1, PLTRST), -/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ -PAD_CFG_GPO(GPP_D15, 0, DEEP), -/* MFR_MODE_DET_STRAP */ -PAD_CFG_GPI(GPP_D16, NONE, PLTRST), -/* TBT_CIO_PWR_EN */ -PAD_CFG_GPO(GPP_E0, 1, DEEP), -/* FPS_INT */ -PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), -/* EC_SLP_S0_CS_N */ -PAD_CFG_GPO(GPP_E6, 1, DEEP), -/* EC_SMI_N */ -PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), -/* TBT_CIO_PLUG_EVENT_N */ -PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), -/* DISP_AUX_P_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E22, 0, PLTRST), -/* DISP_AUX_N_BIAS_GPIO */ -PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* SATA_HDD_PWREN */ -PAD_CFG_GPO(GPP_F4, 1, PLTRST), -/* BIOS_REC */ -PAD_CFG_GPI(GPP_F5, NONE, PLTRST), -/* SD_CD# */ -PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), -/* SD_WP */ -PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), -/* M2_SSD_RST_N */ -PAD_CFG_GPO(GPP_H0, 1, DEEP), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* UART2 RX */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART2 TX */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_CROS_GPIOS(cros_gpios); |