diff options
Diffstat (limited to 'src/mainboard/intel/d945gclf')
| -rw-r--r-- | src/mainboard/intel/d945gclf/Kconfig | 9 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/acpi_tables.c | 30 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/mainboard.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/mainboard_smi.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/mptable.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 8 |
6 files changed, 26 insertions, 27 deletions
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 4532b5c8b2..58609ffd11 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,17 +20,21 @@ config BOARD_INTEL_D945GCLF bool "D945GCLF" select ARCH_X86 - select CPU_INTEL_CORE + select CPU_INTEL_ATOM_230 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945 select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X select BOARD_HAS_FADT + select GENERATE_ACPI_TABLES + select GENERATE_PIRQ_TABLE + select GENERATE_MP_TABLE select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select USE_PRINTK_IN_CAR select AP_IN_SIPI_WAIT @@ -38,6 +42,9 @@ config BOARD_INTEL_D945GCLF select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 + select USE_DCACHE_RAM + select GFXUMA + select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 6b2956d387..8539f0ff26 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -32,6 +32,7 @@ #define OLD_ACPI 0 extern unsigned char AmlCode[]; +void *amlcodeptr = &AmlCode; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif @@ -65,17 +66,10 @@ typedef struct acpi_oemb { } __attribute__((packed)) acpi_oemb_t; #endif -typedef struct acpi_gnvs { - // 0x00 - u16 osys; - u8 smif; - u8 reserved[13]; - // 0x10 - u8 mpen; -} __attribute__((packed)) acpi_gnvs_t; +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" #if OLD_ACPI -void acpi_create_oemb(acpi_oemb_t *oemb) +static void acpi_create_oemb(acpi_oemb_t *oemb) { acpi_header_t *header = &(oemb->header); unsigned long tolud; @@ -114,13 +108,14 @@ void acpi_create_oemb(acpi_oemb_t *oemb) }; #endif -void acpi_create_gnvs(acpi_gnvs_t *gnvs) +static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->mpen = 1; + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) { #define HPET_ADDR 0xfed00000ULL acpi_header_t *header = &(hpet->header); @@ -212,7 +207,6 @@ unsigned long write_acpi_tables(unsigned long start) #if OLD_ACPI acpi_oemb_t *oemb; #endif - acpi_gnvs_t *gnvs; acpi_header_t *ssdt; acpi_header_t *dsdt; @@ -279,10 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_create_facs(facs); + int len = ((acpi_header_t *) amlcodeptr)->length; dsdt = (acpi_header_t *) current; - current += ((acpi_header_t *) AmlCode)->length; - memcpy((void *) dsdt, (void *) AmlCode, - ((acpi_header_t *) AmlCode)->length); + current += len; + memcpy((void *) dsdt, amlcodeptr, len); #if OLD_ACPI for (i=0; i < dsdt->length; i++) { @@ -299,14 +293,14 @@ unsigned long write_acpi_tables(unsigned long start) /* Pack GNVS into the ACPI table area */ for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current); + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes break; } } /* And fill it */ - acpi_create_gnvs(current); + acpi_create_gnvs((global_nvs_t *)current); current += 0x100; ALIGN_CURRENT; diff --git a/src/mainboard/intel/d945gclf/mainboard.c b/src/mainboard/intel/d945gclf/mainboard.c index c7cc9d9708..a94b2061cd 100644 --- a/src/mainboard/intel/d945gclf/mainboard.c +++ b/src/mainboard/intel/d945gclf/mainboard.c @@ -20,10 +20,9 @@ #include <device/device.h> #include <console/console.h> #include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" -int add_northbridge_resources(struct lb_memory *mem); - int add_mainboard_resources(struct lb_memory *mem) { return add_northbridge_resources(mem); diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c index afe9eee57b..fc4c508194 100644 --- a/src/mainboard/intel/d945gclf/mainboard_smi.c +++ b/src/mainboard/intel/d945gclf/mainboard_smi.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <arch/romcc_io.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" /* The southbridge SMI handler checks whether gnvs has a diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index db5ee12b01..5d57f3d743 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -25,7 +25,7 @@ #include <string.h> #include <stdint.h> -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 131145cfb9..073ca8efdb 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -83,7 +83,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/reset_test.c" #include "northbridge/intel/i945/errata.c" #include "northbridge/intel/i945/debug.c" @@ -216,8 +215,6 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include "southbridge/intel/i82801gx/cmos_failover.c" - #include <cbmem.h> // Now, this needs to be included because it relies on the symbol @@ -228,6 +225,8 @@ static void early_ich7_init(void) // #include "lib/cbmem.c" +#include "cpu/intel/model_106cx/cache_as_ram_disable.c" + void real_main(unsigned long bist) { u32 reg32; @@ -337,7 +336,7 @@ void real_main(unsigned long bist) * day. */ if (resume_backup_memory) - memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); @@ -345,4 +344,3 @@ void real_main(unsigned long bist) #endif } -#include "cpu/intel/model_106cx/cache_as_ram_disable.c" |