diff options
Diffstat (limited to 'src/mainboard/google')
4 files changed, 25 insertions, 3 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 2d7eaec6c6..04e6e994be 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -42,7 +42,16 @@ chip soc/amd/cezanne .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), + /* + * b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH, + * but eSPI gets configured in verstage which is in RO. + * We have already locked RO for guybrush devices so we need + * make it so x86 coreboot re-initializes the vw_irq_polarity. + * This leaves another problem, verstage also runs in S0i3, but + * we don't run any other x86 coreboot stages, so we need to + * figure out a way to reset the eSPI polarity. + */ + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1), }" # Enable S0i3 support diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h index ea6b93eef2..b8b466b6a8 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -64,6 +64,7 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1} /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 68eb6ea588..69146041e8 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -227,7 +227,13 @@ chip soc/amd/picasso .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + /* + * b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH, + * but eSPI gets configured in verstage which is in RO. + * We have already locked RO for zork devices so we need + * make it so x86 coreboot re-initializes the vw_irq_polarity. + */ + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), }" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4bb42dea1c..96e66aff1c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -225,7 +225,13 @@ chip soc/amd/picasso .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + /* + * b/160595155 - These should really be ESPI_VW_IRQ_LEVEL_HIGH, + * but eSPI gets configured in verstage which is in RO. + * We have already locked RO for zork devices so we need + * make it so x86 coreboot re-initializes the vw_irq_polarity. + */ + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), }" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" |