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-rw-r--r--src/mainboard/google/brya/variants/xol/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb
index f840afed9e..0547dca8fe 100644
--- a/src/mainboard/google/brya/variants/xol/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xol/overridetree.cb
@@ -261,10 +261,10 @@ chip soc/intel/alderlake
end
end
device ref pcie4_0 on
- # Enable CPU PCIE RP 1 using CLK 1
+ # Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1,
- .clk_src = 1,
+ .clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
probe STORAGE STORAGE_NVME