diff options
Diffstat (limited to 'src/mainboard/google/veyron_speedy')
16 files changed, 1015 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig new file mode 100644 index 0000000000..ee22cc9b47 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -0,0 +1,83 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_VEYRON_SPEEDY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ID_SUPPORT + select BOARD_ROMSIZE_KB_4096 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select EC_SOFTWARE_SYNC + select RAM_CODE_SUPPORT + select SOC_ROCKCHIP_RK3288 + select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_BOOTBLOCK_INIT + select HAVE_HARD_RESET + select RETURN_FROM_VERSTAGE + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/veyron_speedy + +config MAINBOARD_PART_NUMBER + string + default "Veyron_Speedy" + +config MAINBOARD_VENDOR + string + default "Google" + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0 + +config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US + int + default 100 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRAM_SIZE_MB + int + default 2048 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + +endif # BOARD_GOOGLE_VEYRON_SPEEDY diff --git a/src/mainboard/google/veyron_speedy/Makefile.inc b/src/mainboard/google/veyron_speedy/Makefile.inc new file mode 100644 index 0000000000..b56af8c38e --- /dev/null +++ b/src/mainboard/google/veyron_speedy/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += romstage.c +romstage-y += sdram_configs.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_speedy/board.h b/src/mainboard/google/veyron_speedy/board.h new file mode 100644 index 0000000000..c3d75bd0f2 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/board.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H + +#include <boardid.h> +#include <gpio.h> + +#define PMIC_BUS 0 + +#define GPIO_RESET GPIO(0, B, 5) + +/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */ + +#endif /* __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H */ diff --git a/src/mainboard/google/veyron_speedy/boardid.c b/src/mainboard/google/veyron_speedy/boardid.c new file mode 100644 index 0000000000..513754f048 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/boardid.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <stdlib.h> + +uint8_t board_id(void) +{ + static int id = -1; + static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ + + if (id < 0) { + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "Board ID: %d.\n", id); + } + + return id; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c new file mode 100644 index 0000000000..1e46ed025c --- /dev/null +++ b/src/mainboard/google/veyron_speedy/bootblock.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <assert.h> +#include <bootblock_common.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/i2c.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +void bootblock_mainboard_early_init() +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + } + +} + +void bootblock_mainboard_init(void) +{ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + i2c_init(PMIC_BUS, 400*KHz); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(PMIC_BUS, 1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(PMIC_BUS, 1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ + rkclk_configure_cpu(); + + /* i2c1 for tpm */ + writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + + /* spi2 for firmware ROM */ + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz); + + /* spi0 for chrome ec */ + writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz); + + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c new file mode 100644 index 0000000000..069b28b91a --- /dev/null +++ b/src/mainboard/google/veyron_speedy/chromeos.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_LID GPIO(0, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY GPIO(0, B, 1) +#define GPIO_ECINRW GPIO(0, A, 7) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_LID); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_WP.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_WP); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + gpios->gpios[count].port = GPIO_RECOVERY.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = GPIO_LID.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power:GPIO active high */ + gpios->gpios[count].port = GPIO_POWER.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + /* EC in RW: GPIO active high */ + gpios->gpios[count].port = GPIO_ECINRW.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC in RW", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Reset: GPIO active high (output) */ + gpios->gpios[count].port = GPIO_RESET.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "reset", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get(GPIO_RECOVERY)) + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb new file mode 100644 index 0000000000..be0e58c86d --- /dev/null +++ b/src/mainboard/google/veyron_speedy/devicetree.cb @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + register "vop_id" = "1" + register "framebuffer_bits_per_pixel" = "16" + register "lcd_bl_pwm_gpio" = "GPIO(7, A, 0)" + register "lcd_bl_en_gpio" = "GPIO(7, A, 2)" + register "lcd_power_on_udelay" = "200000" + register "bl_power_on_udelay" = "1000" + register "bl_pwm_to_enable_udelay" = "1000" +end diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c new file mode 100644 index 0000000000..1c7dc7f5ad --- /dev/null +++ b/src/mainboard/google/veyron_speedy/mainboard.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <edid.h> +#include <gpio.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <soc/clock.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <soc/i2c.h> +#include <symbols.h> +#include <vbe.h> + +#include "board.h" + +static void configure_usb(void) +{ + gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ + gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ + gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */ +} + +static void configure_sdmmc(void) +{ + writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0); + + /* use sdmmc0 io, disable JTAG function */ + writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0); + + rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */ + rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */ + + gpio_input(GPIO(7, A, 5)); /* SD_DET */ +} + +static void configure_emmc(void) +{ + writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata); + writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren); + writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd); + + gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ +} + +static void configure_codec(void) +{ + writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */ + i2c_init(2, 400000); /* CODEC I2C */ + + writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); + writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); + + rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */ + + /* AUDIO IO domain 1.8V voltage selection */ + writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel); + rkclk_configure_i2s(12288000); +} + +static void configure_vop(void) +{ + writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); + + /* lcdc(vop) iodomain select 1.8V */ + writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel); + + rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */ + rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */ + rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */ +} + +static void mainboard_init(device_t dev) +{ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */ + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */ + i2c_init(0, 400000); /* PMIC I2C */ + + gpio_output(GPIO_RESET, 0); + + configure_usb(); + configure_sdmmc(); + configure_emmc(); + configure_codec(); + configure_vop(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} diff --git a/src/mainboard/google/veyron_speedy/memlayout.ld b/src/mainboard/google/veyron_speedy/memlayout.ld new file mode 100644 index 0000000000..ead7f47838 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/memlayout.ld @@ -0,0 +1 @@ +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/veyron_speedy/reset.c b/src/mainboard/google/veyron_speedy/reset.c new file mode 100644 index 0000000000..9cbe9c1551 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/reset.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <gpio.h> +#include <reset.h> + +#include "board.h" + +void hard_reset(void) +{ + gpio_output(GPIO_RESET, 1); + while (1); +} diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c new file mode 100644 index 0000000000..201931968a --- /dev/null +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <armv7.h> +#include <assert.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <soc/sdram.h> +#include <soc/clock.h> +#include <soc/pwm.h> +#include <soc/grf.h> +#include <soc/tsadc.h> +#include <stdlib.h> +#include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "timer.h" + +static void regulate_vdd_log(unsigned int mv) +{ + unsigned int duty_ns; + const u32 period_ns = 2000; /* pwm period: 2000ns */ + const u32 max_regulator_mv = 1350; /* 1.35V */ + const u32 min_regulator_mv = 870; /* 0.87V */ + + writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1); + + assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); + + duty_ns = (max_regulator_mv - mv) * period_ns / + (max_regulator_mv - min_regulator_mv); + + pwm_init(1, period_ns, duty_ns); +} + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif + + console_init(); + configure_l2ctlr(); + tsadc_init(); + + /* vdd_log 1200mv is enough for ddr run 666Mhz */ + regulate_vdd_log(1200); +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif + sdram_init(get_sdram_config()); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); + + cbmem_initialize_empty(); + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + +#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) + void *entry = vboot2_load_ramstage(); + if (entry != NULL) + stage_exit(entry); +#endif + + run_ramstage(); +} diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c new file mode 100644 index 0000000000..359375830c --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_configs.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/sdram.h> +#include <string.h> +#include <types.h> + +static struct rk3288_sdram_params sdram_configs[] = { +#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */ +}; + +const struct rk3288_sdram_params *get_sdram_config() +{ + u32 ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) + || sdram_configs[ramcode].dramtype == UNUSED) + die("Invalid RAMCODE."); + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc new file mode 100644 index 0000000000..07161c0dfa --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x35, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xBB, + .trp = 0x8, + .trtw = 0x4, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x6, + .tras = 0x14, + .trc = 0x1D, + .trcd = 0x8, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x200, + .txp = 0x4, + .txpdll = 0xD, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x6, + .tcksrx = 0x6, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x36, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x3AD48890, + .dtpr1 = 0xBB08D8, + .dtpr2 = 0x1002B600, + .mr[0] = 0x840, + .mr[1] = 0x40, + .mr[2] = 0x8, + .mr[3] = 0x0 + }, + .noc_timing = 0x2891E41D, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc new file mode 100644 index 0000000000..f5793d1561 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4B4G1646D-BYK0 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc new file mode 100644 index 0000000000..f42f1b1b8b --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4E8E304ED-EGCE000 chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc new file mode 100644 index 0000000000..06498f7f14 --- /dev/null +++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc @@ -0,0 +1,3 @@ +{ + .dramtype= UNUSED +},
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