diff options
Diffstat (limited to 'src/mainboard/google/ninja')
| -rw-r--r-- | src/mainboard/google/ninja/acpi/chromeos.asl | 31 | ||||
| -rw-r--r-- | src/mainboard/google/ninja/chromeos.c | 12 | ||||
| -rw-r--r-- | src/mainboard/google/ninja/dsdt.asl | 1 | ||||
| -rw-r--r-- | src/mainboard/google/ninja/mainboard.c | 2 |
4 files changed, 13 insertions, 33 deletions
diff --git a/src/mainboard/google/ninja/acpi/chromeos.asl b/src/mainboard/google/ninja/acpi/chromeos.asl deleted file mode 100644 index 814380c763..0000000000 --- a/src/mainboard/google/ninja/acpi/chromeos.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: On Bay Trail we need to encode gpios within the 3 separate banks - * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded - * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery - Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect -}) diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c index baafb6f798..1213266d3f 100644 --- a/src/mainboard/google/ninja/chromeos.c +++ b/src/mainboard/google/ninja/chromeos.c @@ -100,4 +100,14 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); -}
\ No newline at end of file +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl index 6475e1c5cf..a37756ff59 100644 --- a/src/mainboard/google/ninja/dsdt.asl +++ b/src/mainboard/google/ninja/dsdt.asl @@ -44,7 +44,6 @@ DefinitionBlock( #include "acpi/dptf.asl" } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c index a5d171eac7..df9ecfae39 100644 --- a/src/mainboard/google/ninja/mainboard.c +++ b/src/mainboard/google/ninja/mainboard.c @@ -34,6 +34,7 @@ #include "onboard.h" #include <soc/gpio.h> #include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -144,6 +145,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); |