diff options
Diffstat (limited to 'src/mainboard/google/hatch/variants')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 14 |
2 files changed, 12 insertions, 5 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index aaef66365b..f913e77558 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -200,7 +200,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" device i2c 15 on end end end # I2C #0 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index badd978397..769d2abf2e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -28,11 +28,11 @@ static const struct pad_config gpio_table[] = { /* WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* - * TRACKPAD_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. + * TRACKPAD_INT_ODL (wake) + * TODO Combine into single gpio, when ITSS IPCx configuration + * is fixed in FSP. */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_14_WLAN_CLKREQ_ODL */ @@ -97,6 +97,12 @@ static const struct pad_config gpio_table[] = { * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE), + /* + * TRACKPAD_INT_ODL + * TODO Combine into single gpio with invert mode, when ITSS + * IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), /* SATAGP1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2_SSD_PE_WAKE_ODL */ |