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-rw-r--r--src/mainboard/google/brya/variants/joxer/overridetree.cb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb
index 12175c5eae..135041d0a7 100644
--- a/src/mainboard/google/brya/variants/joxer/overridetree.cb
+++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb
@@ -16,6 +16,13 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
+ # Acoustic settings
+ register "acoustic_noise_mitigation" = "1"
+ register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+ register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+ register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+ register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
+
# EMMC Tx CMD Delay
# Refer to EDS-Vol2-42.3.7.
# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.