diff options
Diffstat (limited to 'src/mainboard/dell/s1850')
| -rw-r--r-- | src/mainboard/dell/s1850/Config.lb | 174 | ||||
| -rw-r--r-- | src/mainboard/dell/s1850/Options.lb | 228 |
2 files changed, 0 insertions, 402 deletions
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb deleted file mode 100644 index cc0edc6a8b..0000000000 --- a/src/mainboard/dell/s1850/Config.lb +++ /dev/null @@ -1,174 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8e8b8f80" - register "pirq_e_h" = "0x80808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb deleted file mode 100644 index fb65f8d8e2..0000000000 --- a/src/mainboard/dell/s1850/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -#default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end |