diff options
Diffstat (limited to 'src/mainboard/avalue/eax-785e')
| -rw-r--r-- | src/mainboard/avalue/eax-785e/acpi_tables.c | 2 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/get_bus_conf.c | 8 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/mptable.c | 2 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/platform_cfg.h | 2 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/romstage.c | 4 |
6 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c index 9642bb4e19..fa93842dfc 100644 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ b/src/mainboard/avalue/eax-785e/acpi_tables.c @@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_facs(facs); /* FDAT */ -#if CONFIG_BOARD_HAS_FADT == 1 +#if CONFIG_BOARD_HAS_FADT current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index 20a856e362..fcf0bd9100 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -23,11 +23,11 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX == 1 +#if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -141,14 +141,14 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX == 1 +#if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif } diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 7f55c0321a..52befa5a47 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -84,7 +84,7 @@ static void eax_785e(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 6f541a0012..bf5a684446 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index e503585525..1ce1c5141c 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index beea992350..366723580a 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); -#if CONFIG_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); |