diff options
Diffstat (limited to 'src/mainboard/artecgroup/dbe61')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/Config.lb | 75 | ||||
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/Options.lb | 6 | ||||
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/auto.c | 75 | ||||
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/mainboard.c | 40 |
4 files changed, 88 insertions, 108 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb index b9d0e15f39..48e0fec450 100644 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ b/src/mainboard/artecgroup/dbe61/Config.lb @@ -125,32 +125,69 @@ config chip.h chip northbridge/amd/lx register "irqmap" = "0xcba5" - register "setupflash" = "1" device apic_cluster 0 on chip cpu/amd/model_lx device apic 0 on end end end device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536_lx - register "enable_gpio0_inta" = "1" - register "enable_ide_nand_flash" = "1" - register "enable_uarta" = "1" - register "audio_irq" = "11" - register "usbf4_irq" = "5" - register "usbf5_irq" = "5" - register "usbf6_irq" = "5" - register "usbf7_irq" = "5" - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio + + device pci 1.0 on end # Host Bridge + + chip drivers/pci/realmode + device pci 1.1 on end # VGA + register "rom_address" = "0xfffc0000" # at the beginning of 256k + end + + device pci 1.2 off end # AES + chip southbridge/amd/cs5536_lx + register "enable_ide_nand_flash" = "0" + + register "isa_irq" = "0" + #register "flash_irq" = "14" + + ## IDE IRQ + register "enable_ide_irq" = "0" + + register "audio_irq" = "5" + register "usb_irq" = "7" + + register "uart0_irq" = "0" + register "uart1_irq" = "4" + + ## PCI INTA ... INTD and their GPIO pins + ## int==0: disable + register "pci_int[0]" = "0" + register "pci_int[1]" = "10" + register "pci_int[2]" = "0" + register "pci_int[3]" = "0" + register "pci_int_pin[0]" = "0" + register "pci_int_pin[1]" = "7" + register "pci_int_pin[2]" = "0" + register "pci_int_pin[3]" = "0" + + + # Keyboard Emulation Logic IRQs + # Enable keyboard IRQ2 + register "enable_kel_keyb_irq" = "0" + # Enable mouse IRQ12 + register "enable_kel_mouse_irq" = "0" + # Configure KEL Emulation IRQ, 0 to disable + register "kel_emul_irq" = "0" + + device pci f.0 on end # ISA Bridge + device pci f.1 on end # Flash controller + device pci f.2 off end # IDE controller + device pci f.3 on end # Audio device pci f.4 on end # OHCI device pci f.5 on end # EHCI - register "unwanted_vpci[0]" = "0" # End of list has a zero - end - end + device pci f.6 off end # UDC controller + device pci f.7 off end # OTG controller + end + chip drivers/pci/rtl8139 + device pci d.0 on end # Realtek LAN + register "nic_irq" = "10" + end + end end diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb index ec4c78c330..b42f0d04a7 100644 --- a/src/mainboard/artecgroup/dbe61/Options.lb +++ b/src/mainboard/artecgroup/dbe61/Options.lb @@ -40,6 +40,9 @@ uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses VIDEO_MB ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 @@ -47,6 +50,9 @@ default ROM_SIZE = 256*1024 ### ### Build options ### +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=0 +default VIDEO_MB=8 ## ## Build code for the fallback boot diff --git a/src/mainboard/artecgroup/dbe61/auto.c b/src/mainboard/artecgroup/dbe61/auto.c index 866f6e4752..1dba629381 100644 --- a/src/mainboard/artecgroup/dbe61/auto.c +++ b/src/mainboard/artecgroup/dbe61/auto.c @@ -37,24 +37,6 @@ static inline unsigned int fls(unsigned int x) return r; } - - - -/* sdram parameters for OLPC: - row address = 13 - col address = 9 - banks = 4 - dimm0size=128MB - d0_MB=1 (module banks) - d0_cb=4 (component banks) - do_psz=4KB (page size) - Trc=10 (clocks) (ref2act) - Tras=7 (act2pre) - Trcd=3 (act2cmd) - Trp=3 (pre2act) - Trrd=2 (act2act) - Tref=17.8ms - */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * @@ -65,49 +47,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr_t msr; unsigned char module_banks, val; - -#if 0 //GX3 - msr = rdmsr(MC_CF07_DATA); - - /* get module banks (sides) per dimm, SPD byte 5 */ - module_banks = 1; - module_banks >>= 1; - msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); - msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); - - /* get component banks per module bank, SPD byte 17 */ - val = 4; - val >>= 2; - msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); - - /* get the module bank density, SPD byte 31 */ - /* this is multiples of 8 MB */ - /* actually it is 2^x*4, where x is the value you put in */ - /* for OLPC, set default size */ - /* dimm size - hardcoded 128Mb */ - val = 5; - msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); - - /* page size = 2^col address */ - val = 2; /* 4096 bytes */ - msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); - - print_debug("computed msr.hi "); - print_debug_hex32(msr.hi); - print_debug("\r\n"); - - /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ - /* well, it may be close. It's about 200,000 ticks */ - msr.lo = 0x00003000; - wrmsr(MC_CF07_DATA, msr); - -#endif - - msr.hi = 0x00005012; - msr.lo = 0x05000040; + msr.hi = 0x10075012; + msr.lo = 0x00000040; wrmsr(MC_CF07_DATA, msr); //GX3 @@ -140,17 +81,17 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) #include "northbridge/amd/lx/raminit.c" #include "sdram/generic_sdram.c" -#define PLLMSRhi 0x00001490 -#define PLLMSRlo 0x02000030 -#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) -#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) +/* CPU and GLIU mult/div */ +#define PLLMSRhi 0x0000039C +/* Hold Count - how long we will sit in reset */ +#define PLLMSRlo 0x00DE0000 + #include "northbridge/amd/lx/pll_reset.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c" + static void msr_init(void) { - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c index c95ca159f4..5a8fb6b469 100644 --- a/src/mainboard/artecgroup/dbe61/mainboard.c +++ b/src/mainboard/artecgroup/dbe61/mainboard.c @@ -4,35 +4,31 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> #include "chip.h" +#define DIVIL_LBAR_GPIO 0x5140000c -static void init(struct device *dev) +static void init_gpio() { - unsigned bus = 0; - unsigned devNic = PCI_DEVFN(0xd, 0); - unsigned devUsb = PCI_DEVFN(0xf, 4); - device_t usb = NULL, nic = NULL; - unsigned char irqUsb = 0xa, irqNic = 0xb; + msr_t msr; + printk_debug("Initializing GPIO module...\n"); + + // initialize the GPIO LBAR + msr.lo = GPIO_BASE; + msr.hi = 0x0000f001; + wrmsr(DIVIL_LBAR_GPIO, msr); + msr = rdmsr(DIVIL_LBAR_GPIO); + printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); +} +static void init(struct device *dev) +{ + // BOARD-SPECIFIC INIT printk_debug("ARTECGROUP DBE61 ENTER %s\n", __FUNCTION__); - // FIXME: do we need to initialize USB OHCI this way? - printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n", - __FUNCTION__, bus, devUsb, irqUsb); - - // initialize the USB controller - usb = dev_find_slot(bus, devUsb); - if (!usb) printk_err("Could not find USB\n"); - else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb); - - printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n", - __FUNCTION__, bus, devNic, irqNic); - - // initialize the Realtek NIC - nic = dev_find_slot(bus, devNic); - if (!nic) printk_err("Could not find USB\n"); - else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic); + init_gpio(); printk_debug("ARTECGROUP DBE61 EXIT %s\n", __FUNCTION__); } |