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-rw-r--r--src/mainboard/amd/inagua/mainboard.c24
-rw-r--r--src/mainboard/amd/inagua/mptable.c41
-rw-r--r--src/mainboard/amd/olivehill/mainboard.c27
-rw-r--r--src/mainboard/amd/olivehill/mptable.c55
-rw-r--r--src/mainboard/amd/parmer/mainboard.c27
-rw-r--r--src/mainboard/amd/parmer/mptable.c56
-rw-r--r--src/mainboard/amd/south_station/mainboard.c19
-rw-r--r--src/mainboard/amd/south_station/mptable.c37
-rw-r--r--src/mainboard/amd/thatcher/mainboard.c27
-rw-r--r--src/mainboard/amd/thatcher/mptable.c56
-rw-r--r--src/mainboard/amd/union_station/mainboard.c19
-rw-r--r--src/mainboard/amd/union_station/mptable.c37
12 files changed, 212 insertions, 213 deletions
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 1bf74a6431..bd963203e3 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -3,6 +3,21 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
+ [0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x10, 0x11, 0x12, 0x13
+};
static void init_gpios(void)
{
@@ -31,11 +46,20 @@ static void init_gpios(void)
gpio_100_write8(0x32, 0x48);
}
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
+
/* Inagua mainboard specific setting */
init_gpios();
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7a189166ae..df3452a871 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -1,25 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,
- [0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x50] = 0x10,0x11,0x12,0x13
-};
+#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
@@ -46,13 +32,6 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -66,23 +45,23 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c
index 221e52a1ed..f605b3f138 100644
--- a/src/mainboard/amd/olivehill/mainboard.c
+++ b/src/mainboard/amd/olivehill/mainboard.c
@@ -1,12 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
static void mainboard_enable(struct device *dev)
{
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 4761728927..5555a33675 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -1,29 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -46,7 +29,6 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -73,17 +55,6 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -97,27 +68,27 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
index 285b1b9ea2..2651ecf748 100644
--- a/src/mainboard/amd/parmer/mainboard.c
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -1,12 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/*************************************************
* enable the dedicated function in parmer board.
*************************************************/
static void mainboard_enable(struct device *dev)
{
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index c7aa69eee6..5e8f9f17b6 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -1,29 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -46,7 +29,6 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -72,18 +54,6 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -96,27 +66,27 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index b25a4b53aa..f29b846a80 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -4,6 +4,23 @@
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
/**
* Southstation using SB GPIO 17/18 to control the Red/Green LED
@@ -31,6 +48,8 @@ static void southstation_led_init(void)
**********************************************/
static void mainboard_enable(struct device *dev)
{
+ pirq_setup();
+
southstation_led_init();
/*
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index f7400de389..df3452a871 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -1,21 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
+#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
@@ -42,13 +32,6 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -62,23 +45,23 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index d71f2d578f..bdc66ad349 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -2,9 +2,34 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
+static const u8 mainboard_picr_data[] = {
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
/*************************************************
* enable the dedicated function in thatcher board.
*************************************************/
@@ -12,6 +37,8 @@ static void mainboard_enable(struct device *dev)
{
msr_t msr;
+ pirq_setup();
+
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(1 << 28);
wrmsr(LS_CFG_MSR, msr);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index bc091e5125..5e8f9f17b6 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -1,29 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[] = {
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -46,7 +29,6 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -72,18 +54,6 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -96,27 +66,27 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 43dde04c63..81541f37f5 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -3,13 +3,32 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
+ pirq_setup();
+
/*
* Initialize ASF registers to an arbitrary address because someone
* long ago set things up this way inside the SPD read code. The
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index f7400de389..df3452a871 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -1,21 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
+#include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v)
{
@@ -42,13 +32,6 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -62,23 +45,23 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 21:31:34 +0000