6 files changed, 83 insertions, 1 deletions

diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig
index 88c4d0a824..b76c87adb7 100644
--- a/src/mainboard/amd/chausie/Kconfig
+++ b/src/mainboard/amd/chausie/Kconfig
@@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
+	select EC_ACPI
 	select SOC_AMD_SABRINA
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select AMD_SOC_CONSOLE_UART
diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc
index 1e1b6d49d6..2560886710 100644
--- a/src/mainboard/amd/chausie/Makefile.inc
+++ b/src/mainboard/amd/chausie/Makefile.inc
@@ -2,6 +2,7 @@
 
 bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
+bootblock-y += ec.c
 
 romstage-y += port_descriptors.c
 
diff --git a/src/mainboard/amd/chausie/bootblock.c b/src/mainboard/amd/chausie/bootblock.c
index c1d9dd488a..1ca5617814 100644
--- a/src/mainboard/amd/chausie/bootblock.c
+++ b/src/mainboard/amd/chausie/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <soc/espi.h>
+#include "ec.h"
 #include "gpio.h"
 
 void bootblock_mainboard_early_init(void)
@@ -10,3 +11,8 @@ void bootblock_mainboard_early_init(void)
 
 	espi_switch_to_spi1_pads();
 }
+
+void bootblock_mainboard_init(void)
+{
+	chausie_ec_init();
+}
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 85e9c08f7e..4a0c5b056e 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -2,7 +2,15 @@
 
 chip soc/amd/sabrina
 	register "common_config.espi_config" = "{
-		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN,
+		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
+		.generic_io_range[0] = {
+			.base = 0x3f8,
+			.size = 8,
+		},
+		.generic_io_range[1] = {
+			.base = 0x600,
+			.size = 256,
+		},
 		.io_mode = ESPI_IO_MODE_QUAD,
 		.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
 		.crc_check_enable = 1,
diff --git a/src/mainboard/amd/chausie/ec.c b/src/mainboard/amd/chausie/ec.c
new file mode 100644
index 0000000000..ac484b2174
--- /dev/null
+++ b/src/mainboard/amd/chausie/ec.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/acpi/ec.h>
+#include "ec.h"
+
+#define CHAUSIE_EC_CMD		0x666
+#define CHAUSIE_EC_DATA		0x662
+
+#define EC_GPIO_3_ADDR		0xA3
+#define EC_GPIO_LOM_RESET_AUX	(1 << 1)
+
+#define EC_GPIO_7_ADDR		0xA7
+#define EC_GPIO_DT_PWREN	(1 << 2)
+#define EC_GPIO_WWAN_MODULE_RST	(1 << 5)
+
+#define EC_GPIO_8_ADDR		0xA8
+#define EC_GPIO_SMBUS0_EN	(1 << 0)
+
+#define EC_GPIO_A_ADDR		0xAA
+#define EC_GPIO_WWAN_PWREN	(1 << 3)
+#define EC_GPIO_M2_SSD0_PWREN	(1 << 6)
+#define EC_GPIO_LOM_PWREN	(1 << 7)
+
+#define EC_GPIO_C_ADDR		0xAC
+#define EC_GPIO_DT_N_WLAN_SW	(1 << 1)
+#define EC_GPIO_MP2_SEL		(1 << 2)
+#define EC_GPIO_WWAN_N_LOM_SW	(1 << 3)
+
+static void configure_ec_gpio(void)
+{
+	uint8_t tmp;
+
+	tmp = ec_read(EC_GPIO_3_ADDR);
+	tmp |= EC_GPIO_LOM_RESET_AUX;
+	ec_write(EC_GPIO_3_ADDR, tmp);
+
+	tmp = ec_read(EC_GPIO_7_ADDR);
+	tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN;
+	ec_write(EC_GPIO_7_ADDR, tmp);
+
+	tmp = ec_read(EC_GPIO_8_ADDR);
+	tmp |= EC_GPIO_SMBUS0_EN;
+	ec_write(EC_GPIO_8_ADDR, tmp);
+
+	tmp = ec_read(EC_GPIO_A_ADDR);
+	tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN;
+	ec_write(EC_GPIO_A_ADDR, tmp);
+
+	tmp = ec_read(EC_GPIO_C_ADDR);
+	tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW;
+	ec_write(EC_GPIO_C_ADDR, tmp);
+}
+
+void chausie_ec_init(void)
+{
+	ec_set_ports(CHAUSIE_EC_CMD, CHAUSIE_EC_DATA);
+	configure_ec_gpio();
+}
diff --git a/src/mainboard/amd/chausie/ec.h b/src/mainboard/amd/chausie/ec.h
new file mode 100644
index 0000000000..d053566d08
--- /dev/null
+++ b/src/mainboard/amd/chausie/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CHAUSIE_EC_H
+#define CHAUSIE_EC_H
+
+void chausie_ec_init(void);
+
+#endif /* CHAUSIE_EC_H */