7 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index cc41ec8631..1d821faf4d 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -19,7 +19,7 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "Ids.h"
 #include "OptionsIds.h"
 #include "heapManager.h"
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 883df6c6bb..6191cb1070 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -21,8 +21,8 @@ if BOARD_AMD_OLIVEHILLPLUS
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select CPU_AMD_AGESA_00730F01
-	select NORTHBRIDGE_AMD_AGESA_00730F01
+	select CPU_AMD_PI_00730F01
+	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_AGESA_AVALON
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/amd/olivehillplus/agesawrapper.c b/src/mainboard/amd/olivehillplus/agesawrapper.c
index 45670bdce4..9d433db4cc 100644
--- a/src/mainboard/amd/olivehillplus/agesawrapper.c
+++ b/src/mainboard/amd/olivehillplus/agesawrapper.c
@@ -22,7 +22,7 @@
 #include <config.h>
 #include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "cpuRegisters.h"
 #include "cpuCacheInit.h"
 #include "cpuApicUtilities.h"
@@ -36,7 +36,7 @@
 #include "heapManager.h"
 #include "FchPlatform.h"
 #include "Fch.h"
-#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/amd/pi/s3_resume.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include "hudson.h"
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb
index a00e2ba823..aec71f9d72 100644
--- a/src/mainboard/amd/olivehillplus/devicetree.cb
+++ b/src/mainboard/amd/olivehillplus/devicetree.cb
@@ -16,18 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
-chip northbridge/amd/agesa/00730F01/root_complex
+chip northbridge/amd/pi/00730F01/root_complex
 	device cpu_cluster 0 on
-		chip cpu/amd/agesa/00730F01
+		chip cpu/amd/pi/00730F01
 			device lapic 0 on  end
 		end
 	end
 
 	device domain 0 on
 		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/00730F01 # CPU side of HT root complex
+		chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
 
-			chip northbridge/amd/agesa/00730F01 # PCI side of HT root complex
+			chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
 				device pci 0.0 on  end # Root Complex
 				device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
 				device pci 1.1 on  end # Internal Multimedia
@@ -37,7 +37,7 @@ chip northbridge/amd/agesa/00730F01/root_complex
 				device pci 2.3 on  end # Realtek NIC
 				device pci 2.4 on  end # Edge Connector
 				device pci 2.5 on  end # Edge Connector
-			end	#chip northbridge/amd/agesa/00730F01
+			end	#chip northbridge/amd/pi/00730F01
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0
@@ -70,6 +70,6 @@ chip northbridge/amd/agesa/00730F01/root_complex
 				{ {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses
 			}"
 
-		end #chip northbridge/amd/agesa/00730F01 # CPU side of HT root complex
+		end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
 	end #domain
-end #northbridge/amd/agesa/00730F01/root_complex
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 15bcd3dfa4..b74dac6218 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -40,7 +40,7 @@ DefinitionBlock (
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
 	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/agesa/00730F01/acpi/cpu.asl>
+	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
 	#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
@@ -65,7 +65,7 @@ DefinitionBlock (
 
 		Device(PCI0) {
 			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/00730F01/acpi/northbridge.asl>
+			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
 			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 6073fd4322..f4fbb92906 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -23,8 +23,8 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <cpu/amd/pi/s3_resume.h>
 #include "agesawrapper.h"
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 5f018a757c..5230f7dfa3 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -31,11 +31,11 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include "agesawrapper.h"
-#include <northbridge/amd/agesa/agesawrapper_call.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
-#include "cpu/amd/agesa/s3_resume.h"
+#include "cpu/amd/pi/s3_resume.h"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {