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-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c10
-rw-r--r--src/mainboard/amd/dinar/buildOpts.c4
-rw-r--r--src/mainboard/amd/dinar/romstage.c4
-rw-r--r--src/mainboard/amd/inagua/romstage.c4
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c10
-rw-r--r--src/mainboard/amd/olivehill/buildOpts.c2
-rw-r--r--src/mainboard/amd/olivehill/romstage.c4
-rw-r--r--src/mainboard/amd/parmer/buildOpts.c2
-rw-r--r--src/mainboard/amd/parmer/romstage.c4
-rw-r--r--src/mainboard/amd/persimmon/romstage.c4
-rw-r--r--src/mainboard/amd/serengeti_cheetah/irq_tables.c4
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c12
-rw-r--r--src/mainboard/amd/south_station/romstage.c4
-rw-r--r--src/mainboard/amd/thatcher/buildOpts.c2
-rw-r--r--src/mainboard/amd/thatcher/romstage.c4
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c10
-rw-r--r--src/mainboard/amd/torpedo/buildOpts.c4
-rw-r--r--src/mainboard/amd/torpedo/romstage.c4
-rw-r--r--src/mainboard/amd/union_station/romstage.c4
19 files changed, 48 insertions, 48 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 5c5b44fe73..e6646f520f 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -107,10 +107,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 958764eaaf..3aa4e91c34 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -33,8 +33,8 @@
* @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
*/
#include <stdlib.h>
-#include "AGESA.h"
-#include "CommonReturns.h"
+#include "AGESA.h"
+#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 1156ec4625..842b4f0ec7 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
if(boot_cpu()) {
post_code(0x34);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 489e81f9ef..468f896b78 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 278a3bd50f..13470e2fb1 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 98151a29ef..5aa176891a 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -250,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
-//#include "KeralaInstall.h"
+//#include "KeralaInstall.h"
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 718a0575d8..326a41ab8c 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
int i;
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 3db1e47a5e..a2b0f87983 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -251,7 +251,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-//#include "VirgoInstall.h"
+//#include "VirgoInstall.h"
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 7bd3984dcc..7c143f4fde 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -59,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index b0fd12ccb5..5d530b787e 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
index 0dd0daccdf..4d42f478ee 100644
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
@@ -98,13 +98,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
}
//pci bridge
- printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n");
+ printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 09b86bb9e2..6388b42e94 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -64,7 +64,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
int ret,i;
u8 device = ctrl->spd_switch_addr;
- printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
+ printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2;
@@ -215,10 +215,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -278,7 +278,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index a66c2b822b..98a042a380 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index bc2ff12512..07ad1684d6 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -251,7 +251,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
-//#include "VirgoInstall.h"
+//#include "VirgoInstall.h"
/* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h"
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index f3108ffcab..8ee42bd5e4 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 6e28cbdd33..f5ac2e0e4b 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 8b34720633..31d1fefef7 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -34,8 +34,8 @@
*/
#include <stdlib.h>
-#include "AGESA.h"
-#include "CommonReturns.h"
+#include "AGESA.h"
+#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index febe1204ba..7ed520a9bc 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x36);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 531d3b43dd..168b57f357 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
AGESAWRAPPER(amdinitmmio);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 11:22:18 +0000